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MC68HC908JW32
Data Sheet
M68HC08 Microcontrollers
MC68HC908JW32 Rev. 5 10/2006
freescale.com
MC68HC908JW32
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 3
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date January, 2005 March, 2005 Revision Level 2 3 First general release. Second general release. Cleaned typos. Table 4-1. Instruction Set Summary -- Updated definition for the STOP instruction and added WAIT instruction. 5.4 I/O Signals -- Removed subsections referring to VDDA and VSSA. Figure 5-1. CGM Block Diagram -- Corrected references to VDDA and VSSA to VDD and VSS. October, 2006 4 Figure 5-3. CGM External Connections -- Removed VDD connection to VDDPLL. Figure 5-10. PLL Filter -- Corrected reference to VSSA to VSS. Figure 7-1. Monitor Mode Circuit -- Corrected VDDPLL connection. Chapter 20 Ordering Information and Mechanical Specifications -- Combined ordering information and mechanical specifications. Updated package dimensions to the latest available at time of publication. October, 2006 5 1.7.2 Analogy Power Supply (VDDPLL and VSSPLL) -- Reworked for clarity. Description Page Number(s) -- -- 48 64 56 63 72 92 219
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MC68HC908JW32 Data Sheet, Rev. 5 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 5 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 6 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 9 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 10 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 11 USB 2.0 FS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Chapter 12 PS2 Clock Generator (PS2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Chapter 13 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Chapter 14 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Chapter 15 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Chapter 16 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 17 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Chapter 18 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 219
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 5
List of Chapters
MC68HC908JW32 Data Sheet, Rev. 5 6 Freescale Semiconductor
Table of Contents
Chapter 1 General Description
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.7.11 1.7.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analogy Power Supply (VDDPLL and VSSPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Regulator Supply (REG25V, REG33V, and VSS33) . . . . . . . . . . . . . . . . . . Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input/Output (I/O) Pins (PTA7-PTA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Input/Output (I/O) Pins (PTB5, PTB1, PTB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Input/Output (I/O) Pins (PTC3-PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Input/Output (I/O) Pins (PTD7-PTD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Input/Output (I/O) Pins (PTE7-PTE2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 19 19 20 21 21 21 21 21 22 22 22 22 22 22 22 22
Chapter 2 Memory
2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 33 33 33 34 34 35 35 36 38
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Table of Contents
Chapter 3 Configuration Registers (CONFIG)
3.1 3.2 3.3 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 40 41
Chapter 4 Central Processor Unit (CPU)
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 43 44 44 45 45 46 47 47 47 47 47 48 53
Chapter 5 Clock Generator Module (CGM)
5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 55 57 57 58 59 59 60 62 62 63 64 64 64 64 64 64
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5.4.6 5.4.7 5.4.8 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 5.8 5.8.1 5.8.2 5.8.3
CGM VCO Clock Output (CGMVCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64 64 64 65 65 67 68 68 69 69 70 70 70 70 71 71 71 72
Chapter 6 System Integration Module (SIM)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Clock Start-up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.6 Universal Serial Bus (USB) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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73 75 75 76 76 76 76 77 77 78 78 79 79 79 79 79 80 80 80 80 81 82 82 83 83 83
Table of Contents
6.5.3 6.5.4 6.5.5 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.7.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85 85 85 85 85 87 88 88 89 90
Chapter 7 Monitor ROM (MON)
7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 8 Timer Interface Module (TIM)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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105 105 105 106 107 107 108 108 108 109 109 110 110 111 111 111 112
8.7 8.8 8.8.1 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5
TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Clock Pin (PTC1/TCLK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112 112 112 112 113 114 115 115 118
Chapter 9 Timebase Module (TBM)
9.1 9.2 9.3 9.4 9.5 9.6 9.6.1 9.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122 123 124 124 124
Chapter 10 Serial Peripheral Interface Module (SPI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Pin Name Conventions and I/O Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 125 125 126 126 128 128 128 129 130 130 131 132 133 134 135 137 137 137 137 137
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Table of Contents
10.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138 138 138 138 139 140 140 140 141 143
Chapter 11 USB 2.0 FS Module
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 USB Module Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 USB Endpoint Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 USB Requestor Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4.1 Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4.2 Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 Endpoint Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5.1 OUT endpoint Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5.2 IN endpoint Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 USB Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 USB Control Register (USBCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 USB Status Register (USBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.3 USB Status Interrupt Mask Register (USIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.4 USB Endpoint 0 Control/Status Register (UEP0CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.5 USB Endpoint 1-4 Control Status Register (UEP1CSR-UEP4CSR) . . . . . . . . . . . . . . . . 11.5.6 USB Endpoint 1-4 Data Size Register (UEP1DSR-UEP4DSR) . . . . . . . . . . . . . . . . . . . . 11.5.7 USB Endpoint 1/2 and 3/4 Base Pointer Register (UEP12BPR-UEP34BPR). . . . . . . . . . 11.5.8 USB Interface Control Register (UINTFCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.9 USB Endpoint 0 Data Register 7-0 (UE0D7-UE0D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 145 146 146 147 147 148 149 149 149 150 150 150 151 153 154 155 156 157 159 159 160 160
Chapter 12 PS2 Clock Generator (PS2CLK)
12.1 12.2 12.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 PS2 Clock Generator Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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Chapter 13 Input/Output (I/O) Ports
13.1 13.2 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.4 13.4.1 13.4.2 13.5 13.5.1 13.5.2 13.6 13.6.1 13.6.2 13.7 13.7.1 13.7.2 13.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Option Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Option Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pullup Control Register (PULLCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 168 168 168 170 170 170 172 172 173 174 174 174 176 176 178 180 180 180 181
Chapter 14 External Interrupt (IRQ)
14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PTE3/D- Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Option Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 183 183 185 186 186 186 187
Chapter 15 Keyboard Interrupt Module (KBI)
15.1 15.2 15.3 15.4 15.4.1 15.5 15.5.1 15.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 189 189 190 191 192 192 193
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15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
193 193 193 193
Chapter 16 Computer Operating Properly (COP)
16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.4 16.5 16.6 16.7 16.7.1 16.7.2 16.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGMRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 195 196 196 196 196 196 196 197 197 197 197 197 198 198 198 198 198
Chapter 17 Low-Voltage Inhibit (LVI)
17.1 17.2 17.3 17.3.1 17.3.2 17.3.3 17.3.4 17.4 17.5 17.6 17.6.1 17.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low VDD Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 199 199 200 200 200 200 201 201 201 201 201
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Chapter 18 Break Module (BRK)
18.1 18.2 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.4 18.4.1 18.4.2 18.5 18.5.1 18.5.2 18.5.3 18.5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMI and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 203 204 204 204 204 205 205 205 205 205 205 206 206 207
Chapter 19 Electrical Specifications
19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal RC Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB DC Electrical Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program/Erase Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 209 210 210 211 212 212 213 213 214 214 214 215
Chapter 20 Ordering Information and Mechanical Specifications
20.1 20.2 20.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 15
Table of Contents
MC68HC908JW32 Data Sheet, Rev. 5 16 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC908JW32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
1.2 Features
Features of the MC68HC908JW32 include: * High-performance M68HC08 architecture * Fully upward-compatible object code with M6805, M146805, and M68HC05 Families * 8-MHz internal bus frequency * 88-kHz internal RC clock for timebase wakeup * 32-Kbytes of on-chip FLASH memory with security(1) * 1-Kbytes of on-chip random-access memory (RAM) * On-chip programming firmware for use with host PC computer * Clock generation module (CGM) * Up to 29 general-purpose 5V input/output (I/O) pins, including: - Keyboard interrupts on 8 pins - Direct drive for normal LED on 3 pins - High current drive for PS/2 connection on 2 pins (with USB module disabled) * Serial peripheral interface module (SPI) * PS2 clock generator module * 16-bit, 2-channel timer interface module (TIM) with selectable rising and falling edges input capture, output compare, PWM capability on each channel, and external clock input option * Full universal serial bus (USB) specification 2.0 full-speed functions: - 12 Mbps data rate - On-chip 3.3V regulator - Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer - 64 bytes endpoint buffer to share among endpoints 1-4 * System protection features: - Optional computer operating properly (COP) reset - Optional low-voltage detection with reset - Illegal opcode detection with reset - Illegal address detection with reset * Low-power design (fully static with stop and wait modes) * Master reset pin with internal pull-up and power-on reset
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH/ROM difficult for unauthorized users. MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 17
General Description
* *
External asynchronous interrupt pin with internal pull-up (IRQ) 48-pin quad flat non-leaded package (QFN)
1.3 MCU Block Diagram
INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PTA7/KBA7 (3) PTA6/KBA6 (3) PTA5/KBA5 (3) PTA4/KBA4 (3) PTA3/KBA3 (3) PTA2/KBA2 (3) PTA1/KBA1 (3) PTA0/KBA0 (3)
CONTROL AND STATUS REGISTERS -- 96 BYTES USER FLASH -- 32,768 BYTES USER RAM -- 1,024 BYTES MONITOR ROM -- 1,472 BYTES USER FLASH VECTOR SPACE -- 48 BYTES OSCILLATORS AND CLOCK GENERATOR MODULE INTERNAL RC OSCILLATOR OSC1 X-TAL OSCILLATOR OSC2 CGMXFC PHASE-LOCKED LOOP PS2 CLOCK GENERATOR MODULE PORTD BREAK MODULE TIMEBASE MODULE PORTB DDRB 2-CHANNEL TIMER INTERFACE MODULE
PORTA
DDRA
PTB5 (2)(4)
PTB1 (2)(4) PTB0 (2)(4) PTC3 PTC2/T1CH1 PTC1/TCLK1 PTC0/T1CH0 PTD7 (2) PTD6 PTD5 PTD4 PTD3 (2) PTD2 (2) PTD1 PTD0 PTE7/SS PTE6/MISO PTE5/MOSI PTE4/SPCLK PTE3/D- (2)(4) PTE2/PS2CLK/D+ (2)(4)
(1)(2)
(1)(3)
IRQ
EXTERNAL INTERRUPT MODULE COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE
SERIAL PERIPHERAL INTERFACE MODULE
USB MODULE USB ENDPOINT
FS USB TRANSCEIVER
DDRD DDRE
RST
SYSTEM INTEGRATION MODULE
VDD VSS VDDPLL VSSPLL REG25V REG33V VSS33
POWER (1) Pin contains integrated pullup device. (2) Pin contains configurable pullup device. (3) Pin contains integrated pullup device when configured as KBI. (4) Pin is open-drain when configured as output, with high current capability.
INTERNAL REGULATOR
Figure 1-1. MC68HC908JW32 Block Diagram
MC68HC908JW32 Data Sheet, Rev. 5 18 Freescale Semiconductor
PORTE
PORTC
DDRC
LOW-VOLTAGE INHIBIT MODULE
Pin Assignments
1.4 Pin Assignments
PTC2/T1CH1 PTA2/KBA2 PTA3/KBA3 PTA4/KBA4 PTA5/KBA5 PTA1/KBA1 PTA6/KBA6 REG25V
37
38
39
40
41
42
43
44
45
46
47
PTA0/KBA0 NC NC PTC1/TCLK1 PTC3 PTB5 PTC0/T1CH0 PTE7/SS PTE6/MISO PTE5/MOSI PTE4/SPCLK NC
48
RESET
VDD
IRQ
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
PTA7/KBA7 VDDPLL CGMXFC VSSPLL REG33V PTE3/D- PTE2/PS2CLK/D+ VSS33 PTB1 PTB0 OSC2 OSC1
NC
NC
NC
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
NC NC = No Connection
Figure 1-2. 48-Pin QFN Pin Assignment
1.5 Clock Tree
Figure 1-3 shows the clock tree diagram for the MC68HC908JW32.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 19
General Description
88-kHz IRC PS[2:0] BCS CGM XTAL Clock CGMXCLK /2 CGMOUT /3 CGMVCLK PLL USB SIM /2 PTC1/TCLK1 TIMER
TBM
CPU
RAM
FLASH
KBI
BREAK
PS2CLK
SPI
Figure 1-3. Clock Tree Diagram
1.6 Power Management
Figure 1-4 shows the power management diagram for MC68HC908JW32.
VDD
GPIO Pad Ring USB SIE
CPU CORE 2.5V Regulator 2.5V
RAM
FLASH
TBM
TIMER REG25V
SIM
BREAK
PS2CLK
SPI POR Circuitry
CGM PLL 2.5V Regulator 2.5V
OSC
LVI Circuitry VDDPLL
VSSPLL USB PHY 3.3V Regulator VSS VSS33 3.3V REG33V
Figure 1-4. Power Management Diagram
MC68HC908JW32 Data Sheet, Rev. 5 20 Freescale Semiconductor
Pin Function
1.7 Pin Function
1.7.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
MCU
VDD VSS
C1 0.1 F
+ C2
VDD
NOTE: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing VSS must be grounded for proper MCU operation.
1.7.2 Analogy Power Supply (VDDPLL and VSSPLL)
VDDPLL is the internal voltage regulator supply for the CGM module of the device. It is recommended that a decoupling capacitor be connected between the VDDPLL and VSSPLL pins placing it as close to the pins as possible.
1.7.3 Internal Voltage Regulator Supply (REG25V, REG33V, and VSS33)
VREG25 is the internal core voltage regulator supply. VREG33 and VSS33 are the internal USB voltage regulator supply.
1.7.4 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 21
General Description
1.7.5 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. A schmitt-trigger and a spike filter is associated with this pin so that the device is more robust to EMC noise.This pin also contains an internal pullup resistor.
1.7.6 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor.
1.7.7 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter connection for the on-chip PLL.
1.7.8 Port A Input/Output (I/O) Pins (PTA7-PTA0)
PTA7-PTA0 are special function, bidirectional ports pins. These pins are shared with KBI module.
1.7.9 Port B Input/Output (I/O) Pins (PTB5, PTB1, PTB0)
PTB5, PTB1-PTB0 are special function, bidirectional ports pins. These pins can be programmable as open-drain output with high current sourcing capability and has built-in programmable pull up resistor.
1.7.10 Port C Input/Output (I/O) Pins (PTC3-PTC0)
PTC0-PTC3 are bidirectional ports pins. PTC0-PTC2 are shared with TIMER channel 0, channel 1 and TCLK1 pins respectively.
1.7.11 Port D Input/Output (I/O) Pins (PTD7-PTD0)
PTD7-PTD0 are bidirectional ports pins. Pullup option are associated with PTD2, 3 and 7. The option is default enabled after reset.
1.7.12 Port E Input/Output (I/O) Pins (PTE7-PTE2)
PTE7-PTE2 are special function, bidirectional ports pins. PTE2-PTE3 are shared with USB 2.0 FS module. PTE2 is shared with PS2 clock module. PTE4-PTE7 are shared with SPI module.
MC68HC908JW32 Data Sheet, Rev. 5 22 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: * 32,768 bytes of user FLASH * 1,024 bytes of RAM * 64 bytes of USB buffer RAM * 48 bytes of user-defined vectors * 1,472 bytes of monitor ROM
2.2 Input/Output I/O Section
Addresses $0000-$005F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses: * $1090; PLL control registers, PTCL * $1091; PLL bandwidth control register, PBWC * $1092; PLL multiplier select register high, PMSH * $1093; PLL multiplier select register low, PMSL * $1094; PLL VCO range select register, PMRS * $1095; PLL Reference divider select register, PMDS * $FE00; Break status register, BSR * $FE01; Reset status register, RSR * $FE02; Reserved * $FE03; Break flag control register, BFCR * $FE04; Interrupt status register 1, INT1 * $FE05; Interrupt status register 2, INT2 * $FE06; Interrupt status register 2, INT3 * $FE07; Reserved * $FE08; FLASH control register, FLCR * $FE09; FLASH block protect register, FLBPR * $FE0A; Reserved * $FE0B; Reserved * $FE0C; Break Address Register High, BRKH * $FE0D; Break Address Register Low, BRKL * $FE0E; Break status and control register, BRKSCR * $FFFF; COP control register, COPCTL
2.3 Monitor ROM
The 1024 bytes at addresses $FA00-$FDFF and 448 bytes at addresses $FE10-$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 23
Memory $0000 $005F $0060 $045F $0460 $0FFF $1000 $103F $1040 $108F $1090 $1095 $1096 $6FFF $7000 $EFFF $F000 $F9FF $FA00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF
I/O Registers 96 Bytes RAM 1,024 Bytes Unimplemented 2,976 Bytes USB Buffer RAM 64 Bytes Unimplemented 80 Bytes CGM Control Registers 6 bytes Unimplemented 24,426 FLASH 32,768 Bytes Unimplemented 3,559 Bytes Monitor ROM 1 1,024 Bytes Break Status Register (BSR) Reset Status Register (RSR) Reserved Break Flag Control Register (BFCR) Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Reserved FLASH Control Register (FLCR) FLASH Block Protect Register (FLBPR) Reserved Reserved Break Address High Register (BRKH) Break Address Low Register (BRKL) Break Status and Control Register (BRKSCR) LVI Status Register (LVISR) Monitor ROM 2 448 Bytes FLASH Vectors 48 Bytes
Figure 2-1. Memory Map
MC68HC908JW32 Data Sheet, Rev. 5 24 Freescale Semiconductor
Monitor ROM Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: $0002 Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: $0004 Data Direction Register A Write: (DDRA) Reset: Read: Data Direction Register B Write: (DDRB) Reset: Read: $0006 Data Direction Register C Write: (DDRC) Reset: Read: Data Direction Register D Write: (DDRD) Reset: Read: $0008 Port E Data Register Write: (PTE) Reset: Read: Data Direction Register E Write: (DDRE) Reset: Read: $000A Timer 1 Status and Control Write: Register (T1SC) Reset: Read: $000B Reserved Write: Read: Timer 1 Counter Register Write: High (T1CNTH) Reset: 0 DDRD7 0 PTE7 0 DDRD6 0 PTE6 0 DDRD5 0 PTE5 0 DDRD4 0 PTE4 PTD7 PTD6 PTD5 Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset PTB5 Unaffected by reset PTC3 Unaffected by reset PTD4 PTD3 PTD2 PTD1 PTD0 PTC2 PTC1 PTC0 PTB1 PTB0
$0001
$0003
Unaffected by reset DDRA7 0* DDRA6 0 DDRA5 0 DDRB5 0* 0 0 0 0 DDRC3 0 DDRD3 0 PTE3 0 DDRC2 0 DDRD2 0 PTE2 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0
$0005
$0007
Unaffected by reset DDRE7 0 TOF 0 0 R DDRE6 0 TOIE 0 R DDRE5 0 TSTOP 1 R DDRE4 0 0 TRST 0 R 0 R DDRE3 0 0 DDRE2 0 PS2 0 R 0 PS1 0 R 0 PS0 0 R
$0009
Bit15 0
Bit14 0
Bit13 0
Bit12 0 R
Bit11 0 = Reserved
Bit10 0
Bit9 0
Bit8 0
$000C
= Unimplemented
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 25
Memory Addr. $000D Register Name Read: Timer 1 Counter Register Write: Low (T1CNTL) Reset: Read: $000E Timer 1 Counter Modulo Write: Register High (T1MODH) Reset: Read: Timer 1 Counter Modulo Write: Register Low (T1MODL) Reset: Read: $0010 Timer 1 Channel 0 Status and Write: Control Register (T1SC0) Reset: Read: Timer 1 Channel 0 Register Write: High (T1CH0H) Reset: Read: $0012 Timer 1 Channel 0 Register Write: Low (T1CH0L) Reset: Read: Timer 1 Channel 1 Status and Write: Control Register (T1SC1) Reset: Timer 1 Channel 1 Read: Register High Write: (T1CH1H) Reset: Timer 1 Channel 1 Read: Register Low Write: (T1CH1L) Reset: Bit 7 Bit7 0 Bit15 1 Bit7 1 CH0F 0 0 Bit15 6 Bit6 0 Bit14 1 Bit6 1 CH0IE 0 Bit14 5 Bit5 0 Bit13 1 Bit5 1 MS0B 0 Bit13 4 Bit4 0 Bit12 1 Bit4 1 MS0A 0 Bit12 3 Bit3 0 Bit11 1 Bit3 1 ELS0B 0 Bit11 2 Bit2 0 Bit10 1 Bit2 1 ELS0A 0 Bit10 1 Bit1 0 Bit9 1 Bit1 1 TOV0 0 Bit9 Bit 0 Bit0 0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
$000F
$0011
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Indeterminate after reset CH1F 0 0 Bit15 CH1IE 0 Bit14 0 0 Bit13 MS1A 0 Bit12 ELS1B 0 Bit11 ELS1A 0 Bit10 TOV1 0 Bit9 CH1MAX 0 Bit8
$0013
$0014
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0015
Indeterminate after reset 0 0 KBIE7 0 TBIF 0 0 0 KBIE6 0 TBR2 0 PS2IF 0 = Unimplemented 0 0 KBIE5 0 TBR1 0 PRE 0 0 0 KBIE4 0 TBR0 0 CSEL1 0 R KEYF 0 KBIE3 0 0 TACK 0 CSEL0 0 = Reserved 0 ACKK 0 KBIE2 0 TBIE 0 PS2IEN 0 IMASKK 0 KBIE1 0 TBON 0 CLKEN 0 MODEK 0 KBIE0 0 R 0 PS2EN 0
Keyboard Status and Control Read: $0016 Register Write: (KBSCR) Reset: $0017 Read: Keyboard Interrupt Enable Write: Register (KBIER) Reset: Read: $0018 Timebase Control Register Write: (TBCR) Reset:
$0019
PS2 Clock Generator Read: PSTATUS Control and Satus Write: Register (PS2CSR) Reset: 0
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 26 Freescale Semiconductor
Monitor ROM Addr. $001A Register Name Port Option Read: Control Register 1 Write: (POCR1) Reset: Port Option Read: Control Register 2 Write: (POCR2) Reset: IRQ Option Read: Control Register Write: (IOCR) Reset: Read: Configuration Register 2 Write: (CONFIG2) Reset: Read: IRQ Status and Control Write: Register (ISCR) Reset: Read: $001F Configuration Register Write: (CONFIG) Reset: Read: Reserved Write: Read: Pullup Control Register Write: (PULLCR) Reset: Read: $003F Reserved Write: USB Endpoint 0 Read: Data Register 0 Write: (UE0D0) Reset: USB Endpoint 0 Read: Data Register 1 Write: (UE0D1) Reset: USB Endpoint 0 Read: Data Register 2 Write: (UE0D2) Reset: USB Endpoint 0 Read: Data Register 3 Write: (UE0D3) Reset: Bit 7 6 5 LEDB5 0 0 0 0 0 0 0 0 0 PTD7PD 0 0 0 PTD3PD 0 0 0 PTD2PD 0 0 0 DPPULLEN 0 PTE3IF 4 3 2 1 LEDB1 0 PTE3P 0 PTE3IE Bit 0 LEDB0 0 PTE2P 0 IRQPD
$001B
$001C
$001D
STOP_ XCLKEN 0 0 0 COPRS 0 0 0 0 LVISTOP 0 0 0 0 LVIRSTD 0
STOP_RC CLKEN 0 0 0 LVIPWRD 0 0 0 IRQF 0
R 0 0 ACK 0 SSREC 0
VREG33D 0 IMASK 0 STOP 0
URSTD 0 MODE 0 COPD 0
$001E
One-time writable register after each reset. $0020 to $003D R R R R R R R R
$003E
PULL5EN 0 R 0 R 0 R 0 R 0 R 0 R
PULL1EN 0 R
PULL0EN 0 R
UE0D07_OUT UE0D06_OUT UE0D05_OUT UE0D04_OUT UE0D03_OUT UE0D02_OUT UE0D01_OUT UE0D00_OUT UE0D07_IN UE0D06_IN UE0D05_IN UE0D04_IN UE0D03_IN UE0D02_IN UE0D01_IN UE0D00_IN
$0040
Unaffected by reset
UE0D17_OUT UE0D16_OUT UE0D15_OUT UE0D14_OUT UE0D13_OUT UE0D12_OUT UE0D11_OUT UE0D10_OUT UE0D17_IN UE0D16_IN UE0D15_IN UE0D14_IN UE0D13_IN UE0D12_IN UE0D11_IN UE0D10_IN
$0041
Unaffected by reset
UE0D27_OUT UE0D26_OUT UE0D25_OUT UE0D24_OUT UE0D23_OUT UE0D22_OUT UE0D21_OUT UE0D20_OUT UE0D27_IN UE0D26_IN UE0D25_IN UE0D24_IN UE0D23_IN UE0D22_IN UE0D21_IN UE0D20_IN
$0042
Unaffected by reset
UE0D37_OUT UE0D36_OUT UE0D35_OUT UE0D34_OUT UE0D33_OUT UE0D32_OUT UE0D31_OUT UE0D30_OUT UE0D37_IN UE0D36_IN UE0D35_IN UE0D34_IN UE0D33_IN UE0D32_IN UE0D31_IN UE0D30_IN
$0043
Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 27
Memory Addr. $0044 Register Name USB Endpoint 0 Read: Data Register 4 Write: (UE0D4) Reset: USB Endpoint 0 Read: Data Register 5 Write: (UE0D5) Reset: USB Endpoint 0 Read: Data Register 6 Write: (UE0D6) Reset: USB Endpoint 0 Read: Data Register 7 Write: (UE0D7) Reset: Read: $0048 Unimplemented Write: Read: $0049 Unimplemented Write: Read: $004A Unimplemented Write: Read: $004B Unimplemented Write: Reset: $004C Read: SPI Control Register Write: (SPCR) Reset: SPI Status and Control Read: Register Write: (SPSCR) Reset: Read: SPI Data Register Write: (SPDR) Reset: Read: $004F Reserved Write: Read: $0050 Reserved Write: SPRIE 0 SPRF 0 R7 T7 R 0 ERRIE 0 R6 T6 SPMSTR 1 OVRF 0 R5 T5 CPOL 0 MODF 0 R4 T4 CPHA 1 SPTE 1 R3 T3 SPWOM 0 MODFEN 0 R2 T2 SPE 0 SPR1 0 R1 T1 SPTIE 0 SPR0 0 R0 T0 Bit 7
UE0D47_IN
6
UE0D46_IN
5
UE0D45_IN
4
UE0D44_IN
3
UE0D43_IN
2
UE0D42_IN
1
UE0D41_IN
Bit 0
UE0D40_IN
UE0D47_OUT UE0D46_OUT UE0D45_OUT UE0D44_OUT UE0D43_OUT UE0D42_OUT UE0D41_OUT UE0D40_OUT
Unaffected by reset
UE0D57_OUT UE0D56_OUT UE0D55_OUT UE0D54_OUT UE0D53_OUT UE0D52_OUT UE0D51_OUT UE0D50_OUT UE0D57_IN UE0D56_IN UE0D55_IN UE0D54_IN UE0D53_IN UE0D52_IN UE0D51_IN UE0D50_IN
$0045
Unaffected by reset
UE0D67_OUT UE0D66_OUT UE0D65_OUT UE0D64_OUT UE0D63_OUT UE0D62_OUT UE0D61_OUT UE0D60_OUT UE0D67_IN UE0D66_IN UE0D65_IN UE0D64_IN UE0D63_IN UE0D62_IN UE0D61_IN UE0D60_IN
$0046
Unaffected by reset
UE0D77_OUT UE0D76_OUT UE0D75_OUT UE0D74_OUT UE0D73_OUT UE0D72_OUT UE0D71_OUT UE0D70_OUT UE0D77_IN UE0D76_IN UE0D75_IN UE0D74_IN UE0D73_IN UE0D72_IN UE0D71_IN UE0D70_IN
$0047
Unaffected by reset
$004D
$004E
Unaffected by reset R R R R R R R R
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 28 Freescale Semiconductor
Monitor ROM Addr. $0051 Register Name Read: USB Control Register Write: (USBCR) Reset: Read: $0052 USB Status Register Write: (USBSR) Reset: Read: USB Status Interrupt Mask Write: Register (USIMR) Reset: Read: $0054 USB EPO Control/Status Write: Register (UEP0CSR) Reset: Read: USB EP1 Control/Status Write: Register (UEP1CSR) Reset: Read: $0056 USB EP2 Control/Status Write: Register (UEP2CSR) Reset: Read: USB EP3 Control/Status Write: Register (UEP3CSR) Reset: USB EP4 Control/Status Read: Register Write: (UEP4CSR) Reset: Read: USB EP1 Data Size Register Write: (UEP1DSR) Reset: Read: $005A USB EP2 Data Size Register Write: (UEP2DSR) Reset: Read: USB EP3 Data Size Register Write: (UEP3DSR) Reset: Read: $005C USB EP4 Data Size Register Write: (UEP4DSR) Reset: USB EP 1/2 Base Pointer Read: Register Write: (UEP12BPR) Reset: 0 0 Bit 7 USBEN 0 CONFIG 0 0 0
EP0_STALL
6
USBCLKEN
5 TFC4IE 0 SETUP 0 SETUPIE 0
DSIZE1_OUT DSIZE1_IN
4 TFC3IE 0 SOF 0 SOFIE 0
DSIZE0_OUT DSIZE0_IN
3 TFC2IE 0
CONFIG_CHG
2 TFC1IE 0 USBRST 0 USBRESETIE 0
TFRC_IN
1 TFC0IE 0 RESUMEF 0
Bit 0 0 RESUME 0 SUSPND 0
0
0 CONFIG_ CHGIE 0
DVALID_IN
$0053
RESUMESUSPNDIE FIE 0
DVALID_OUT
0
DSIZE3_OUT DSIZE3_IN
0
DSIZE2_OUT DSIZE2_IN
0
TFRC_OUT
0 MODE1 0 MODE1 0 MODE1 0 MODE1 0
0 MODE0 0 MODE0 0 MODE0 0 MODE0 0 DSIZE6
0 0 STALL 0 0 STALL 0 0 STALL 0 0 STALL 0 DSIZE5 0 DSIZE5 0 DSIZE5 0 DSIZE5 0 BASE21 0
0 DIR 0 DIR 0 DIR 0 DIR 0 DSIZE4 0 DSIZE4 0 DSIZE4 0 DSIZE4 0 BASE20 0 R
0 SIZE1 0 SIZE1 0 SIZE1 0 SIZE1 0 DSIZE3 0 DSIZE3 0 DSIZE3 0 DSIZE3 0
0 SIZE0 0 SIZE0 0 SIZE0 0 SIZE0 0 DSIZE2 0 DSIZE2 0 DSIZE2 0 DSIZE2 0 BASE12
0 DVALID 0 DVALID 0 DVALID 0 DVALID 0 DSIZE1 0 DSIZE1 0 DSIZE1 0 DSIZE1 0 BASE11 0
0 TFRC 0 TFRC 0 TFRC 0 TFRC 0 DSIZE0 0 DSIZE0 0 DSIZE0 0 DSIZE0 0 BASE10 0
$0055
$0057
$0058
$0059
0
0 DSIZE6 0 DSIZE6
$005B
0
0 DSIZE6 0 BASE22
$005D
0
0 = Unimplemented
0 = Reserved
0
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 29
Memory Addr. $005E Register Name USB EP 3/4 Base Pointer Read: Register Write: (UEP34BPR) Reset: Read: $005F USB Interface Control Write: Register (UINTFCR) Reset: Read: PLL Control Register Write: (PTCL) Reset: PLL Bandwidth Control Read: Register Write: (PBWC) Reset: Read: $1092 PLL Multiplier Select Write: Register High (PMSH) Reset: Read: PLL Multiplier Select Write: Register Low (PMSL) Reset: Read: $1094 PLL VCO Range Select Write: Register (PMRS) Reset: Read: PLL Reference Divider Write: Select Register (PMDS) Reset: Read: Break Status Register Write: (BSR) Reset: Read: Reset Status Register Write: (RSR) POR: Read: $FE02 Reserved Write: Read: Break Flag Control Write: Register (BFCR) Reset: 0 Bit 7 6 BASE42 0 0 EP4INT 0 PLLF 0 LOCK 0 0 0 MUL6 1 VRS6 1 0 0 0 5 BASE41 0 4 BASE40 0 EP3INT 0 0 0 3 2 BASE32 0 EP2INT 0 0 1 BASE31 0 Bit 0 BASE30 0 EP1INT 0
$1090
PLLIE 0 AUTO 0 0 0 MUL7 0 VRS7 0 0 0
PLLON 1 ACQ 0 0 0 MUL5 0 VRS5 0 0 0
BCS 0 0 0 0 0 MUL4 0 VRS4 0 0 0
PRE1 0 0 0 MUL11 0 MUL3 0 VRS3 0 RDS3 0
PRE0 0 0 0 MUL10 0 MUL2 0 VRS2 0 RDS2 0
VPR1 0 0 0 MUL9 0 MUL1 0 VRS1 0 RDS1 0 SBSW See note 0
VPR0 0 R
$1091
MUL8 0 MUL0 0 VRS0 0 RDS0 1
$1093
$1095
$FE00
R
R
R
R
R
R
R
Note: Writing a logic 0 clears SBSW. POR 1 R PIN 0 R COP 0 R ILOP 0 R ILAD 0 R USB 0 R LVI 1 R 0 0 R $FE01
$FE03
BCFE 0
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 30 Freescale Semiconductor
Monitor ROM Addr. $FE04 Register Name Read: Interrupt Status Register 1 Write: (INT1) Reset: Read: $FE05 Interrupt Status Register 2 Write: (INT2) Reset: Read: Interrupt Status Register 3 Write: (INT3) Read: $FE07 Reserved Write: Read: FLASH Control Register Write: (FLCR) Reset: Read: $FE09 FLASH Block Protect Write: Register (FLBPR) Reset: Read: $FE0A Reserved Write: Read: $FE0B Reserved Write: Read: Break Address High Write: Register (BRKH) Reset: Read: $FE0D Break Address low Write: Register (BRKL) Reset: Read: Break Status and Control Write: Register (BRKSCR) Reset: Read: $FE0F LVI Sttatusl Register Write: (LVISR) Reset: Read: COP Control Register Write: (COPCTL) Reset: = Unimplemented Bit 7 IF6 R 0 IF14 R 0 0 R 0 R 6 IF5 R 0 IF13 R 0 0 R 0 R 5 IF4 R 0 IF12 R 0 0 R 0 R 4 IF3 R 0 IF11 R 0 0 R 0 R 3 IF2 R 0 IF10 R 0 0 R 0 R 2 IF1 R 0 IF9 R 0 0 R 0 R 1 0 R 0 IF8 R 0 0 R 0 R Bit 0 0 R 0 IF7 R 0 IF15 R 0 R
$FE06
0 0 BPR7 0 R
0 0 BPR6 0 R
0 0 BPR5 0 R
0 0 BPR4 0 R
$FE08
HVEN 0 BPR3 0 R
MASS 0 BPR2 0 R
ERASE 0 BPR1 0 R
PGM 0 BPR0 0 R
R
R
R
R
R
R
R
R
$FE0C
Bit15 0 Bit7 0 BRKE 0 LVIOUT 0
Bit14 0 Bit6 0 BRKA 0 0 0
Bit13 0 Bit5 0 0 0 0 0
Bit12 0 Bit4 0 0 0 0 0
Bit11 0 Bit3 0 0 0 0 0
Bit10 0 Bit2 0 0 0 0 0
Bit9 0 Bit1 0 0 0 0 0
Bit8 0 Bit0 0 0 0 0 0
$FE0E
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset R = Reserved U = Unaffected by reset
$FFFF
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 31
Memory
Table 2-1 is a list of vector locations. Table 2-1. Vector Addresses
Vector Lowest Vector IF15 Address $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector Timebase Vector (High) Timebase Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) Reserved Reserved Reserved Reserved Reserved Reserved PS2 Interrupt Vector (High) PS2 Interrupt Vector (Low) Timer 1 Overflow Vector (High) Timer 1 Overflow Vector (Low) Timer 1 Channel 1 Vector (High) Timer 1 Channel 1 Vector (Low) Timer 1 Channel 0 Vector (High) Timer 1 Channel 0 Vector (Low) PLL Vector (High) PLL Vector (Low) IRQ Vector (High) IRQ Vector (Low) USB Endpoint Vector (High) USB Endpoint Vector (Low) USB System Vector (High) USB System Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
--
Highest
--
MC68HC908JW32 Data Sheet, Rev. 5 32 Freescale Semiconductor
Random-Access Memory (RAM)
2.4 Random-Access Memory (RAM)
Addresses $0060 through $045F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.5 FLASH Memory
This sub-section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
2.5.1 Functional Description
The FLASH memory consists of an array of 32,768 bytes for user memory plus a block of 48 bytes for user interrupt vectors and one byte for the mask option register. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is defined as 512 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are: * $7000-$EFFF; user memory, 32,768 bytes * $FFD0-$FFFF; user interrupt vectors, 48 bytes Programming tools are available from Freescale. Contact your local Freescale representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 33
Memory
2.5.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operation.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $FE08 Bit 7 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0
Figure 2-3. FLASH Control Register (FLCR) HVEN -- High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected
2.5.3 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 512 consecutive bytes starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Write any data to any FLASH location within the page address range desired. 3. Wait for a time, tnvs (5 s). 4. Set the HVEN bit. 5. Wait for a time terase (20 ms). 6. Clear the ERASE bit.
MC68HC908JW32 Data Sheet, Rev. 5 34 Freescale Semiconductor
FLASH Memory
7. Wait for a time, tnvh (5 s). 8. Clear the HVEN bit 9. After time, trcv (1 s), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
2.5.4 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Write any data to any FLASH location within the FLASH memory address range. 3. Wait for a time, tnvs (5 s). 4. Set the HVEN bit. 5. Wait for a time tme (200 ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100 s). 8. Clear the HVEN bit. 9. After time, trcv (1 s), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
2.5.5 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX800 or $XXC00. Use the following procedure to program a row of FLASH memory. (Figure 2-4 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH location within the address range of the row to be programmed. 3. Wait for a time, tnvs (5 s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (10 s). 6. Write data to the FLASH location to be programmed. 7. Wait for time, tprog (20 s to 40 s). 8. Repeat steps 6 and 7 until all bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5 s). 11. Clear the HVEN bit. 12. After time, trcv (1 s), the memory can be accessed in read mode again.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 35
Memory
This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 9), must not exceed the maximum programming time, tprog max. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
2.5.6 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations. NOTE The 48 bytes of user interrupt vectors ($FFD0-$FFFF) are always protected, regardless of the value in the FLASH block protect register. A mass erase is required to erase these locations.
MC68HC908JW32 Data Sheet, Rev. 5 36 Freescale Semiconductor
FLASH Memory
1
Set PGM bit
Algorithm for programming a row (64 bytes) of FLASH memory
2
Write any data to any FLASH address within the row address range desired
3
Wait for a time, tnvs
4
Set HVEN bit
5
Wait for a time, tpgs
6
Write data to the FLASH address to be programmed
7
Wait for a time, tprog
Completed programming this row? N
9
Y
NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
End of Programming
Figure 2-4. FLASH Programming Flowchart
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 37
Memory
2.5.7 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory.
Address: Read: Write: Reset: $FE09 Bit 7 BPR7 0 6 BPR6 0 5 BPR5 0 4 BPR4 0 3 BPR3 0 2 BPR2 0 1 BPR1 0 Bit 0 BPR0 0
Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Block Protect Bits BPR[7:1] represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0's.
16-bit memory address Start address of FLASH block protect BPR[7:1] 000000000
BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be X000, X200, etc. (at page boundaries -- 512 bytes) within the FLASH memory. Examples of protect start address: Table 2-2 FLASH Block Protect Range
BPR[7:0] $00-$70 $70 or $71 (0111 000x) $72 or $73 (0111 001x) $74 or $75 (0111 010x) Protected Range The entire FLASH memory is protected. $7000 to $FFFF (The entire FLASH memory is protected.) $7200 to $FFFF $7400 to $FFFF and so on... $EE or $EF (1110 111x) $F0 - $FF $EE00 to $FFFF The entire FLASH memory is NOT protected.(1)
1. The 48-byte user vectors ($FFD0-$FFFF), which are always protected.
MC68HC908JW32 Data Sheet, Rev. 5 38 Freescale Semiconductor
Chapter 3 Configuration Registers (CONFIG)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: * Computer operating properly module (COP) * COP timeout period (262,128 or 8176 CGMRCLK cycles) * Low-voltage inhibit (LVI) module power * LVI module reset * LVI module in stop mode * LVI module voltage trip point selection * STOP instruction * Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) * Oscillator during stop mode
Addr. $001D Register Name Read: Configuration Register 2 Write: (CONFIG2) Reset: Read: Configuration Register 1 Write: (CONFIG1) Reset: Bit 7 6 5 STOP_ XCLKEN 0 COPRS 0 0 LVISTOP 0 = Unimplemented 0 LVIRSTD 0 4 STOP_RC CLKEN 0 LVIPWRD 0 0 0 3 2 R 0 SSREC 0 1 VREG33D 0 STOP 0 Bit 0 URSTD 0 COPD 0
$001F
One-time writable register after each reset.
Figure 3-1. CONFIG Registers Summary
3.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration register (CONFIG1) can be written once after each reset but CONFIG2 register can perform multiple write. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 39
Configuration Registers (CONFIG)
3.3 Configuration Register 1 (CONFIG1)
Address: Read: Write: Reset: $001F Bit 7 COPRS 0 6 LVISTOP 0 5 LVIRSTD 0 4 LVIPWRD 0 0 3 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
= Unimplemented
Figure 3-2. Configuration Register 1 (CONFIG1) COPRS -- COP Rate Select COPRS selects the COP time-out period. Reset clears COPRS. (See Chapter 16 Computer Operating Properly (COP).) 1 = COP time out period = 8176 CGMRCLK cycles 0 = COP time out period = 262,128 CGMRCLK cycles LVISTOP -- Low Voltage Inhibit Enable in STOP mode bit When the LVIPWRD bit is clear or the LVIREGD is clear, setting the LVISTOP bit enables the LVI to operate during STOP mode. Reset clears LVISTOP. 1 = Low voltage inhibit enabled during stop mode 0 = Low voltage inhibit disable during stop mode LVIRSTD -- LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module completely. When it is set, LVI trip for VDD is disabled. 1 = LVI module power and LVI trip for VDD disabled 0 = LVI module power and LVI trip for VDD is enabled SSREC -- Short Stop Recovery SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay. 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit. NOTE When the LVISTOP is enabled, the system stabilization time for power on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the enable time for the LVI. There is no period where the MCU is not protected from a low power condition. However, when using the short stop recovery configuration option, the 32 CGMXCLK delay is less than the LVI's turn-on time and there exists a period in start-up where the LVI is not protecting the MCU.
MC68HC908JW32 Data Sheet, Rev. 5 40 Freescale Semiconductor
Configuration Register 2 (CONFIG2)
STOP -- STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Chapter 16 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
3.4 Configuration Register 2 (CONFIG2)
Address: Read: Write: Reset: 0 0 $001D Bit 7 6 5 STOP_ XCLKEN 0 4 STOP_RC CLKEN 0 0 3 2 R 0 1 VREG33D 0 Bit 0 URSTD 0
= Unimplemented
Reset by POR only.
Figure 3-3. Configuration Register 2 (CONFIG2) STOP_XCLKEN -- Crystal Oscillator Stop Mode Enable Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator to continue operating during stop mode, in the other words, SIMOSCEN hold high during STOP mode. When this bit is cleared, the external XTAL oscillator will be disabled during stop mode. Reset clears this bit. 1 = XTAL oscillator enabled during stop mode 0 = XTAL oscillator disabled during stop mode STOP_RCCLKEN -- RC clock Stop Mode Enable Setting STOP_RCCLKEN enables the internal RC clock to continue operating during STOP mode. When this bit is cleared, the internal RC clock will be disabled during STOP mode. Reset clears this bit. 1 = Internal RC clock enabled during stop mode 0 = Internal RC clock disable during stop mode VREG33D -- 3.3V USB Regulator Disable Bit VREG33D disables the USB 3.3V regulator completely. 1 = VREG33 regulator is disabled 0 = VREG33 regulator is enabled URSTD -- USB Reset Disable Bit URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers. Instead, it will generate an interrupt request to CPU. 1 = USB reset generates a interrupt request to CPU 0 = USB reset generates a chip reset
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 41
Configuration Registers (CONFIG)
MC68HC908JW32 Data Sheet, Rev. 5 42 Freescale Semiconductor
Chapter 4 Central Processor Unit (CPU)
4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
Features of the CPU include: * Object code fully upward-compatible with M68HC05 Family * 16-bit stack pointer with stack manipulation instructions * 16-bit index register with x-register manipulation instructions * 8-MHz CPU internal bus frequency * 64-Kbyte program/data memory space * 16 addressing modes * Memory-to-memory data moves without using accumulator * Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions * Enhanced binary-coded decimal (BCD) data handling * Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes * Low-power stop and wait modes
4.3 CPU Registers
Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 43
Central Processor Unit (CPU)
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 4-2. Accumulator (A)
4.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-3. Index Register (H:X)
MC68HC908JW32 Data Sheet, Rev. 5 44 Freescale Semiconductor
CPU Registers
4.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
4.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-5. Program Counter (PC)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 45
Central Processor Unit (CPU)
4.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: Write: Reset: V X X = Indeterminate 6 1 1 5 1 1 4 H X 3 I 1 2 N X 1 Z X Bit 0 C X
Figure 4-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result
MC68HC908JW32 Data Sheet, Rev. 5 46 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
4.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
4.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode
The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock
4.5.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction * Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 47
Central Processor Unit (CPU)
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set. Table 4-1. Instruction Set Summary (Sheet 1 of 6)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
-
IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 - - - - - - REL - - - - - - REL - - - - - - REL
3 3
MC68HC908JW32 Data Sheet, Rev. 5 48 Freescale Semiconductor
Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3 3 3 3
Effect on CCR
Operand
Instruction Set Summary
Table 4-1. Instruction Set Summary (Sheet 2 of 6)
Address Mode Opcode Source Form
BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
VH I NZC
- - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT - IX2 IX1 IX SP1 SP2
24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A
rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR IMM - - - - - - IMM IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI Clear Carry Bit Clear Interrupt Mask
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 49
Cycles
3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary (Sheet 3 of 6)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
M $00 A $00 X $00 H $00 M $00 M $00 M $00
VH I NZC
Clear
DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
--
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr ii ii+1 dd ii dd hh ll ee ff ff ff ee ff
Compare H:X with M
--
Compare X with M
(X) - (M)
--
Decimal Adjust A
(A)10
U--
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1 INH IMM DIR EXT - IX2 IX1 IX SP1 SP2 DIR INH - INH IX1 IX SP1
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
----
Exclusive OR M with A
A (A M)
0--
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff
MC68HC908JW32 Data Sheet, Rev. 5 50 Freescale Semiconductor
Cycles
3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5
Effect on CCR
Operand
Instruction Set Summary
Table 4-1. Instruction Set Summary (Sheet 4 of 6)
Address Mode Opcode Source Form
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX
Operation
Description
VH I NZC
PC Jump Address
Jump
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT - IX2 IX1 IX SP1 SP2 - IMM DIR
BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE
dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Load H:X from M
H:X (M:M + 1)
0--
Load X from M
X (M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DD DIX+ - IMD IX+D DIR INH INH IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
--
38 48 58 68 ff 78 9E68 ff
Logical Shift Right
0 b7 b0
C
--0
34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89
Move Unsigned multiply
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
4 1 1 4 3 5 dd dd 5 4 dd 4 ii dd 4 dd 5 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2
- 0 - - - 0 INH
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1
- - - - - - INH - - - - - - INH - - - - - - INH
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 51
Cycles
2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary (Sheet 5 of 6)
Address Mode Opcode Source Form
PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Pull A from Stack Pull H from Stack Pull X from Stack
Description
SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
VH I NZC
- - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Left through Carry
C b7 b0
--
Rotate Right through Carry
b7 b0
C
--
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable Interrupts, Stop Processing, Refer to MCU Documentation
(M:M + 1) (H:X) I 0; Stop Processing
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
MC68HC908JW32 Data Sheet, Rev. 5 52 Freescale Semiconductor
Cycles
2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Opcode Map
Table 4-1. Instruction Set Summary (Sheet 6 of 6)
Address Mode Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC
SWI
Software Interrupt
- - 1 - - - INH
83
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 8F
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP Enable Interrupts; Wait for Interrupt
H:X (SP) + 1 A (X) (SP) (H:X) - 1 I bit 0; Inhibit CPU clocking until interrupted n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH - - 0 - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) #
? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
4.8 Opcode Map
See Table 4-2.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 53
Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2 1
Effect on CCR
Operand
54
Bit Manipulation DIR DIR
MSB LSB
Central Processor Unit (CPU)
Table 4-2. Opcode Map
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM DIR B EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 E SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 IX F 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4
5 6 7 8 9 A B C D E
F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Chapter 5 Clock Generator Module (CGM)
5.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the base clock signal, CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop (PLL) clock, CGMVCLK, divided by three. CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT/2. The PLL is a frequency generator designed for use with a crystal (4MHz) to generate a base frequency and dividing to a maximum bus frequency of 8MHz.
5.2 Features
Features of the CGM include: * Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference * Low-frequency crystal operation with low-power operation and high-output frequency resolution * Programmable prescaler for power-of-two increases in frequency * Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation * Automatic bandwidth control mode for low-jitter operation * Automatic frequency lock detector * CPU interrupt on entry or exit from locked condition * Configuration register bit to allow oscillator operation during stop mode
5.3 Functional Description
The CGM consists of three major sub-modules: * Oscillator module -- The oscillator module generates the constant reference frequency clock, CGMRCLK (buffered CGMXCLK). * Phase-locked loop (PLL) -- The PLL generates the programmable VCO frequency clock, CGMVCLK. * Base clock selector circuit -- This software-controlled circuit selects either CGMXCLK divided by two or the divided VCO clock, CGMVCLK, divided by three as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 5-1 shows the structure of the CGM. Figure 5-2 is a summary of the CGM registers.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 55
Clock Generator Module (CGM)
OSCILLATOR (OSC) MODULE INTERNAL RC OSC OSC2 CGMXCLK XTAL OSC OSC1 CGMRCLK To SIM ICLK To Timebase Module (TBM)
SIMOSCEN From SIM PHASE-LOCKED LOOP (PLL)
/2
CGMRDV
REFERENCE DIVIDER R
CGMRCLK BCS CLOCK SELECT CIRCUIT
A B1 S* *WHEN S = 1, CGMOUT = B
CGMOUT To SIM SIMDIV2 From SIM
RDS[3:0]
VDD
CGMXFC
VSS VPR[1:0] VRS[7:0] L 2E
/3
CGMVCLK To USB
PHASE DETECTOR
LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR PLL ANALOG
LOCK DETECTOR
AUTOMATIC MODE CONTROL
INTERRUPT CONTROL
CGMINT To SIM
LOCK MUL[11:0] N CGMVDV FREQUENCY DIVIDER
AUTO
ACQ
PLLIE PRE[1:0] 2P
PLLF
CGMPCLK
FREQUENCY DIVIDER
Figure 5-1. CGM Block Diagram
MC68HC908JW32 Data Sheet, Rev. 5 56 Freescale Semiconductor
Functional Description Addr. $1090 Register Name Read: PLL Control Register Write: (PTCL) Reset: PLL Bandwidth Control Read: Register Write: (PBWC) Reset: PLL Multiplier Select Read: Register High Write: (PMSH) Reset: Read: PLL Multiplier Select Register Write: Low (PMSL) Reset: Read: 1095PLL VCO Range Select Write: Register (PMRS) Reset: Bit 7 PLLIE 0 AUTO 0 0 0 MUL7 0 VRS7 0 0 0 6 PLLF 0 LOCK 0 0 0 MUL6 1 VRS6 1 0 0 = Unimplemented NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. 5 PLLON 1 ACQ 0 0 0 MUL5 0 VRS5 0 0 0 4 BCS 0 0 0 0 0 MUL4 0 VRS4 0 0 0 3 PRE1 0 0 0 MUL11 0 MUL3 0 VRS3 0 RDS3 0 R 2 PRE0 0 0 0 MUL10 0 MUL2 0 VRS2 0 RDS2 0 = Reserved 1 VPR1 0 0 0 MUL9 0 MUL1 0 VRS1 0 RDS1 0 MUL8 0 MUL0 0 VRS0 0 RDS0 1 Bit 0 VPR0 0 R
$1091
$1092
$1093
$1094
Read: PLL Reference Divider Select $1095 Write: Register (PMDS) Reset:
Figure 5-2. CGM I/O Register Summary
5.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module. CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also provides the reference clock for the timebase module (TBM). See Chapter 9 Timebase Module (TBM) for detailed description on TBM.
5.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 57
Clock Generator Module (CGM)
5.3.3 PLL Circuits
The PLL consists of these circuits: * Voltage-controlled oscillator (VCO) * Reference divider * Frequency pre-scaler * Modulo VCO frequency divider * Phase detector * Loop filter * Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (125 kHz) times a linear factor, L, and a power-of-two factor, E, or (L x 2E)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a factor, R. The divider's output is the final reference clock, CGMRDV, running at a frequency, fRDV = fRCLK/R. With an external crystal (4MHz), always set R = 1 for specified performance. With an external high-frequency clock source, use R to divide the external frequency to between 1MHz and 8MHz. The VCO's output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a power-of-two factor P (the CGMPCLK) and the modulo divider reduces the VCO clock by a factor, N. The dividers' output is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N x 2P). (See 5.3.6 Programming the PLL for more information.) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 5.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison.
MC68HC908JW32 Data Sheet, Rev. 5 58 Freescale Semiconductor
Functional Description
5.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 5.5.2 PLL Bandwidth Control Register.) * Tracking mode -- In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. (See 5.3.8 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set.
5.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 5.5.2 PLL Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. (See 5.3.8 Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 5.6 Interrupts for information and precautions on using interrupts.) The following conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (See 5.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. (See 5.3.4 Acquisition and Tracking Modes.) * The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 5.8 Acquisition/Lock Time Specifications for more information.) * The LOCK bit is a read-only indicator of the locked state of the PLL. * The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 5.8 Acquisition/Lock Time Specifications for more information.) * CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. (See 5.5.1 PLL Control Register.) The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 59
Clock Generator Module (CGM)
The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. * Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 5.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL). * Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). * The LOCK bit is disabled. * CPU interrupts from the CGM are disabled.
5.3.6 Programming the PLL
The following procedure shows how to program the PLL. NOTE The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency, fBUSDES, or the desired VCO frequency, fVCLKDES; and then solve for the other. The relationship between fBUS and fVCLK is governed by the equation:
f VCLK = 6
x fBUS
2. Choose a practical PLL reference frequency, fRCLK, and the reference clock divider, R. Typically, the reference is 4MHz and R = 1. Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is
2N f VCLK = ----------- ( f RCLK ) R
P
where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 19 Electrical Specifications. Choose the reference divider, R = 1. When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with practical choices of fRCLK, and choose the fRCLK that gives the lowest R.
f VCLKDES f VCLKDES R = round R MAX x ------------------------- - integer ------------------------- f RCLK f RCLK
MC68HC908JW32 Data Sheet, Rev. 5 60 Freescale Semiconductor
Functional Description
3. Calculate N:
R x f VCLKDES N = round ------------------------------------ P f x2
RCLK
4. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS.
2N f VCLK = ----------- ( f RCLK ) R f VCLK
P
f BUS =
---------6
5. Select the VCO's power-of-two range multiplier E, according to this table:
Frequency Range 0 < fVCLK < 9,830,400 9,830,400 fVCLK < 19,660,800 19,660,800 fVCLK < 39,321,600 NOTE: Do not program E to a value of 3. E 0 1 2
6. Select a VCO linear range multiplier, L, where fNOM = 125kHz
f VCLK L = round -------------------------- 2E x f
NOM
7. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL.
f VRS = ( L x 2 )f NOM
E
For proper operation,
f NOM x 2 f VRS - f VCLK -------------------------2
E
8. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application's tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK. NOTE Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 61
Clock Generator Module (CGM)
9. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. NOTE The values for P, E, N, L, and R can only be programmed when the PLL is off (PLLON = 0). Table 5-1 provides numeric examples (numbers are in hexadecimal notation): Table 5-1. Numeric Examples
CGMVCLK 48 MHz CGMPCLK 24 MHz fBUS 8 MHz fRCLK 4 MHz R 1 N 06 P 1 E 2 L 96
5.3.7 Special Programming Exceptions
The programming method described in 5.3.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: * A 0 value for R or N is interpreted exactly the same as a value of 1. * A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See 5.3.8 Base Clock Selector Circuit.
5.3.8 Base Clock Selector Circuit
This circuit is used to select either the oscillator clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The CGMXCLK clock is divided by two while the CGMVCLK is divided by three to correct the duty cycle. The two divided clocks go through a transition control circuit that to change from one clock source to the other. During this time, CGMOUT is held in stasis. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is either one-fourth the frequency of the selected clock (CGMXCLK) or one-sixth the frequency of the selected CGMVCLK clock. The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the divided VCO clock. The divided VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock.
MC68HC908JW32 Data Sheet, Rev. 5 62 Freescale Semiconductor
Functional Description
5.3.9 CGM External Connections
In its typical configuration, the CGMC requires up to nine external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 5-3. Figure 5-3 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * Crystal, X1 * Fixed capacitor, C1 * Tuning capacitor, C2 (can also be a fixed capacitor) * Feedback resistor, RB * Series resistor, RS The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the crystal manufacturer's data for more information regarding values for C1 and C2. Figure 5-3 also shows the external components for the PLL: * Bypass capacitor, CBYP * Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 5.8 Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL performance.)
SIMOSCEN FROM SIM OSC_XCLKEN (FROM CONFIG)
CGMXCLK
MCU
OSC1 OSC2 CGMXFC VSSPLL VDDPLL
RB 2k RS (4-MHZ) 2n2 F X1 C1 C2 100 pF CBYP 0.1 F
Note: Filter network in box can be replaced with a 0.47F capacitor, but will degrade stability.
Figure 5-3. CGM External Connections
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 63
Clock Generator Module (CGM)
5.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
5.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 5.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 5.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 5-3.) NOTE To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network.
5.4.4 Oscillator Output Frequency Signal (CGMXCLK)
CGMXCLK is the oscillator output signal. It runs at the full speed of the oscillator, and is generated directly from the crystal oscillator circuit, the RC oscillator circuit, or the internal oscillator circuit.
5.4.5 CGM Reference Clock (CGMRCLK)
CGMRCLK is a buffered version of CGMXCLK, this clock is the reference clock for the phase-locked-loop circuit.
5.4.6 CGM VCO Clock Output (CGMVCLK)
CGMVCLK is the clock output from the VCO.
5.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by three.
5.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
MC68HC908JW32 Data Sheet, Rev. 5 64 Freescale Semiconductor
CGM Registers
5.5 CGM Registers
The following registers control and monitor operation of the CGM: * PLL control register (PCTL) -- (See 5.5.1 PLL Control Register.) * PLL bandwidth control register (PBWC) -- (See 5.5.2 PLL Bandwidth Control Register.) * PLL multiplier select registers (PMSH and PMSL) -- (See 5.5.3 PLL Multiplier Select Registers.) * PLL VCO range select register (PMRS) -- (See 5.5.4 PLL VCO Range Select Register.) * PLL reference divider select register (PMDS) -- (See 5.5.5 PLL Reference Divider Select Register.)
5.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address: Read: Write: Reset: $1090 Bit 7 PLLIE 0 6 PLLF 0 5 PLLON 1 4 BCS 0 3 PRE1 0 2 PRE0 0 1 VPR1 0 Bit 0 VPR0 0
= Unimplemented
Figure 5-4. PLL Control Register (PCTL) PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF -- PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition NOTE Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 5.3.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 65
Clock Generator Module (CGM)
BCS -- Base Clock Select Bit This read/write bit selects either the oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 5.3.8 Base Clock Selector Circuit.) Reset clears the BCS bit. 1 = CGMVCLK divided by three drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT NOTE PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 5.3.8 Base Clock Selector Circuit.) PRE1 and PRE0 -- Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set. Reset clears these bits. These prescaler bits affects the relationship between the VCO clock and the final system bus clock. Table 5-2. PRE1 and PRE0 Programming
PRE1 and PRE0 00 01 10 11 P 0 1 2 3 Prescaler Multiplier 1 2 4 8
VPR1 and VPR0 -- VCO Power-of-Two Range Select Bits These read/write bits control the VCO's hardware power-of-two range multiplier E that, in conjunction with L (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.4 PLL VCO Range Select Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits. Table 5-3. VPR1 and VPR0 Programming
VPR1 and VPR0 00 01 10 NOTE: Do not program E to a value of 3. E 0 1 2 VCO Power-of-Two Range Multiplier 1 2 4
MC68HC908JW32 Data Sheet, Rev. 5 66 Freescale Semiconductor
CGM Registers
5.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC): * Selects automatic or manual (software-controlled) bandwidth control mode * Indicates when the PLL is locked * In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode * In manual operation, forces the PLL into acquisition or tracking mode
Address: Read: Write: Reset: $1091 Bit 7 AUTO 0 6 LOCK 0 5 ACQ 0 4 0 0 3 0 0 R 2 0 0 = Reserved 1 0 0 Bit 0 R
= Unimplemented
Figure 5-5. PLL Bandwidth Control Register (PBWCR) AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 67
Clock Generator Module (CGM)
5.5.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider.
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented $1092 Bit 7 0 6 0 5 0 4 0 3 MUL11 0 2 MUL10 0 1 MUL9 0 Bit 0 MUL8 0
Figure 5-6. PLL Multiplier Select Register High (PMSH)
Address: Read: Write: Reset: $1093 Bit 7 MUL7 0 6 MUL6 1 5 MUL5 0 4 MUL4 0 3 MUL3 0 2 MUL2 0 1 MUL1 0 Bit 0 MUL0 0
Figure 5-7. PLL Multiplier Select Register Low (PMSL) MUL[11:0] -- Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) A value of $0000 in the multiplier select registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1).
5.5.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO.
Address: Read: Write: Reset: $1094 Bit 7 VRS7 0 6 VRS6 1 5 VRS5 0 4 VRS4 0 3 VRS3 0 2 VRS2 0 1 VRS1 0 Bit 0 VRS0 0
Figure 5-8. PLL VCO Range Select Register (PMRS) VRS[7:0] -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.1 PLL Control Register.), controls the hardware center-of-range frequency, fVRS. VRS[7:0] cannot be written when the PLLON bit in the PCTL is set. (See 5.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
MC68HC908JW32 Data Sheet, Rev. 5 68 Freescale Semiconductor
Interrupts
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 5.3.8 Base Clock Selector Circuit and 5.3.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64. NOTE The VCO range select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock.
5.5.5 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider.
Address: Read: Write: Reset: 0 0 0 0 $1095 Bit 7 0 6 0 5 0 4 0 3 RDS3 0 2 RDS2 0 1 RDS1 0 Bit 0 RDS0 1
= Unimplemented
Figure 5-9. PLL Reference Divider Select Register (PMDS) RDS[3:0] -- Reference Divider Select Bits These read/write bits control the modulo reference divider that selects the reference division factor, R. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) RDS[3:0] cannot be written when the PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (See 5.3.7 Special Programming Exceptions.) Reset initializes the register to $01 for a default divide value of 1. NOTE The reference divider select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). NOTE The default divide value of 1 is recommended for all applications.
5.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the divided VCO clock, CGMVCLK, divided by three can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 69
Clock Generator Module (CGM)
VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. NOTE Software can select the CGMVCLK divided by three as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
5.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
5.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
5.7.2 Stop Mode
If the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) for the selected oscillator is configured to disabled the oscillator in stop mode, then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMOUT, CGMVCLK, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by three driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the oscillator clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. If the oscillator stop mode enable bit is configured for continuous oscillator operation in stop mode, then the phase locked loop is shut off but the CGMXCLK will continue to drive the SIM and other MCU sub-systems.
5.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 6.7.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
MC68HC908JW32 Data Sheet, Rev. 5 70 Freescale Semiconductor
Acquisition/Lock Time Specifications
5.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.
5.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0Hz to 1MHz, the acquisition time is the time taken for the frequency to reach 1MHz 50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at 1MHz and suffers a -100kHz noise hit, the acquisition time is the time taken to return from 900kHz to 1MHz 5kHz. 5kHz = 5% of the 100kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error.
5.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is under user control via the choice of crystal frequency fXCLK and the R value programmed in the reference divider. (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.5 PLL Reference Divider Select Register.) Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. (See 5.8.3 Choosing a Filter.) Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 71
Clock Generator Module (CGM)
5.8.3 Choosing a Filter
As described in 5.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in Figure 5-10 is recommended when using a 4MHz reference clock (CGMRCLK). Figure 5-10 (a) is used for applications requiring better stability. Figure 5-10 (b) is used in low-cost applications where stability is not critical.
CGMXFC CGMXFC
2 k 2n2 nF
100 pF
0.22 F
VSS
(a)
VSS
(b)
Figure 5-10. PLL Filter
MC68HC908JW32 Data Sheet, Rev. 5 72 Freescale Semiconductor
Chapter 6 System Integration Module (SIM)
6.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 6-1. Figure 6-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control * Master reset control, including power-on reset (POR) and COP timeout * Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * CPU enable/disable timing * Modular architecture expandable to 128 interrupt sources Table 6-1 shows the internal signal names used in this section. Table 6-1. Signal Name Conventions
Signal Name ICLK CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W Internal RC oscillator clock Selected oscillator clock from oscillator module PLL VCO output and the divided PLL output CGMVCLK-based or oscillator-based clock output from CGM module (Bus clock = CGMOUT / 2) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal Description
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 73
System Integration Module (SIM)
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM, OSC) SIM COUNTER COP CLOCK
CGMXCLK (FROM CGM) CGMOUT (FROM CGM) /2
VDD INTERNAL PULLUP DEVICE RESET PIN LOGIC
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 6-1. SIM Block Diagram
Addr.
$FE00
Register Name
Read: SIM Break Status Register Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register Write: (SRSR) POR: Read: SIM Break Flag Control Write: Register (SBFCR) Reset:
Bit 7
R 0 POR
6
R 0 PIN 0 R
5
R 0 COP 0 R
4
R 0 ILOP 0 R
3
R 0 ILAD 0 R
2
R 0 USB 0 R
1
SBSW NOTE 0 LVI 0 R
Bit 0
R 0 0 0 R
$FE01
1
BCFE 0
$FE03
= Unimplemented
R
= Reserved
Figure 6-2. SIM I/O Register Summary
MC68HC908JW32 Data Sheet, Rev. 5 74 Freescale Semiconductor
SIM Bus Clock Control and Generation Read: Interrupt Status Register 1 Write: (INT1) Reset: Read: Interrupt Status Register 2 Write: (INT2) Reset: Read: $FE06 Interrupt Status Register 3 Write: (INT3) Reset: IF6 R 0 IF14 R 0 0 R 0 IF5 R 0 IF13 R 0 0 R 0 = Unimplemented IF4 R 0 IF12 R 0 0 R 0 IF3 R 0 IF11 R 0 0 R 0 R IF2 R 0 IF10 R 0 0 R 0 = Reserved IF1 R 0 IF9 R 0 0 R 0 0 R 0 IF8 R 0 0 R 0 0 R 0 IF7 R 0 IF15 R 0
$FE04
$FE05
Figure 6-2. SIM I/O Register Summary
6.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 6-3. This clock can come from either an external oscillator or from the on-chip PLL. (See Chapter 5 Clock Generator Module (CGM).)
OSC2 OSCILLATOR (OSC) MODULE OSC1
CGMXCLK
TO TBM
CGMXCLK SIM COUNTER STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 SYSTEM INTEGRATION MODULE SIMOSCEN IT12 TO REST OF MCU IT23 TO REST OF MCU
CGMRCLK CGMOUT PHASE-LOCKED LOOP (PLL)
/2
BUS CLOCK GENERATORS
SIMDIV2
PTC1 MONITOR MODE USER MODE
Figure 6-3. CGM Clock Signals
6.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by six.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 75
System Integration Module (SIM)
6.2.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
6.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 6.6.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
6.3 Reset and System Initialization
The MCU has these reset sources: * Power-on reset module (POR) * External reset pin (RST) * Computer operating properly module (COP) * Low-voltage inhibit module (LVI) * Illegal opcode * Illegal address * Universal serial bus module (USB) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 6.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 6.7 SIM Registers.)
6.3.1 External Pin Reset
The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 6-2 for details. Figure 6-4 shows the relative timing. Table 6-2. PIN Bit Set Timing
Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
MC68HC908JW32 Data Sheet, Rev. 5 76 Freescale Semiconductor
Reset and System Initialization
CGMXCLK
RST
IAB
PC
VECT H VECT L
Figure 6-4. External Reset Timing
6.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 6-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 6-6). NOTE For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 6-5.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 6-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI USB
INTERNAL RESET
Figure 6-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 6.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 77
System Integration Module (SIM)
At power-on, these events occur: * A POR pulse is generated. * The internal reset signal is asserted. * The SIM enables CGMOUT. * Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. * The pin is driven low during the oscillator stabilization time. * The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES
CGMOUT
RST IRST
IAB
$FFFE
$FFFF
Figure 6-7. POR Recovery 6.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 8176 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ1 pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ1 pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 6.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset.
MC68HC908JW32 Data Sheet, Rev. 5 78 Freescale Semiconductor
SIM Counter
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 6.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. 6.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 6.3.2.6 Universal Serial Bus (USB) Reset The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 2.5s treats that signal as a reset. After the reset is removed, the device will be in the attached, but not yet addressed or configured, state (refer to Section 9.1 USB Devices of the Universal Serial Bus Specification Rev. 2.0). The device must be able to accept the device address via a SET_ADDRESS command (refer to Section 9.4 of the Universal Serial Bus Specification Rev. 2.0) no later than 10ms after the reset is removed. USB reset can be disabled to generate an internal reset. It can be configured to generate IRQ interrupt. (See Chapter 3 Configuration Registers (CONFIG).) NOTE USB reset is disabled when the USB module is disabled by clearing the USBEN bit of the USB address register (UADDR).
6.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
6.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 79
System Integration Module (SIM)
6.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared.
6.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 6.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 6.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
6.5 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts: - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * Reset * Break interrupts
6.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 6-8 shows interrupt entry timing, and Figure 6-9 shows interrupt recovery timing.
MODULE INTERRUPT I-BIT IAB IDB R/W DUMMY DUMMY SP SP - 1 SP - 2 X SP - 3 A SP - 4 CCR VECT H VECT L START ADDR OPCODE
PC - 1[7:0] PC - 1[15:8]
V DATA H
V DATA L
Figure 6-8. Interrupt Entry Timing
MODULE INTERRUPT I-BIT IAB IDB R/W SP - 4 CCR SP - 3 A SP - 2 X SP - 1 SP PC PC + 1 OPCODE OPERAND
PC - 1[15:8] PC - 1[7:0]
Figure 6-9. Interrupt Recovery Timing
MC68HC908JW32 Data Sheet, Rev. 5 80 Freescale Semiconductor
Exception Control
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 6-10.)
FROM RESET
BREAK I BIT SET? INTERRUPT? NO YES
YES
I-BIT SET? NO IRQ1 INTERRUPT? NO YES
AS MANY INTERRUPTS AS EXIST ON CHIP
STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 6-10. Interrupt Processing 6.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 81
System Integration Module (SIM)
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 6-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 6-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 6.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
6.5.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 6-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.
MC68HC908JW32 Data Sheet, Rev. 5 82 Freescale Semiconductor
Exception Control
6.5.2.1 Interrupt Status Register 1
Address: Read: Write: Reset: $FE04 Bit 7 IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 6-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 6-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0 6.5.2.2 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
Figure 6-13. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 6-3. 1 = Interrupt request present 0 = No interrupt request present 6.5.2.3 Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 IF15 R 0
Figure 6-14. Interrupt Status Register 3 (INT3) IF15 -- Interrupt Flag 15 This flag indicates the presence of an interrupt request from the source shown in Table 6-3. 1 = Interrupt request present 0 = No interrupt request present
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 83
System Integration Module (SIM)
Table 6-3. Interrupt Sources
Priority Lowest INT Flag IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5
IF4 IF3 IF2 IF1 -- --
Vector Address $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3
$FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF
Interrupt Source Timebase Keyboard SPI Transmit SPI Receive Reserved Reserved Reserved PS2 Interrupt TIM1 Overflow TIM1 Channel 1 TIM1 Channel 0 PLL IRQ USB Endpoint USB System SWI Reset
Highest
MC68HC908JW32 Data Sheet, Rev. 5 84 Freescale Semiconductor
Low-Power Modes
6.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
6.5.4 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 18 Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
6.5.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
6.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
6.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 6-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 85
System Integration Module (SIM)
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 6-15. Wait Mode Entry Timing Figure 6-16 and Figure 6-17 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 6-16. Wait Recovery from Interrupt or Break
32 CYCLES IAB $6E0B
32 CYCLES RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 6-17. Wait Recovery from Internal Reset
MC68HC908JW32 Data Sheet, Rev. 5 86 Freescale Semiconductor
Low-Power Modes
6.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 6-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 6-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 6-19. Stop Mode Recovery from Interrupt or Break
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 87
System Integration Module (SIM)
6.7 SIM Registers
The SIM has three memory-mapped registers: * SIM Break Status Register (SBSR) -- $FE00 * SIM Reset Status Register (SRSR) -- $FE01 * SIM Break Flag Control Register (SBFCR) -- $FE03
6.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode.
Address: Read: Write: Reset: Note: Writing a logic 0 clears SBSW. R = Reserved $FE00 Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R
Figure 6-20. SIM Break Status Register (SBSR) SBSW -- Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it.
MC68HC908JW32 Data Sheet, Rev. 5 88 Freescale Semiconductor
SIM Registers
6.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address: Read: Write: Reset: 1 0 0 0 0 0 0 0 = Unimplemented $FE01 Bit 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 1 LVI Bit 0 0
USB
Figure 6-21. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR USB -- USB Reset Bit 1 = Last reset caused by USB reset. 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 89
System Integration Module (SIM)
6.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 6-22. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC908JW32 Data Sheet, Rev. 5 90 Freescale Semiconductor
Chapter 7 Monitor ROM (MON)
7.1 Introduction
This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer.
7.2 Features
Features of the monitor ROM include: * Normal user-mode pin functionality * One pin dedicated to serial communication between monitor ROM and host computer * Standard mark/space non-return-to-zero (NRZ) communication with host computer * Execution of code in RAM or ROM * ROM memory security feature(1) * 960 bytes monitor ROM code size ($FC00-$FDFF and $FE10-$FFCE) * Standard monitor mode entry if high voltage, VTST, is applied to IRQ
7.3 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows an example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code allows enabling the PLL to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal. This entry method, which is enabled when IRQ is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode.
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users. MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 91
Monitor ROM (MON)
RST 0.1 F VDD
HC908JW32
VDD
0.1 F VDDPLL 0.1 F VSSPLL VREG 4.9152MHz/9.8304MHz (50% DUTY) OSC1 1k MUST BE USED IF SW2 IS AT POSITION C. CONNECT TO OSC1, WITH OSC2 UNCONNECTED. EXT OSC 4.9152MHz 6-30 pF MAX232 1 1 F + 3 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 2 74HC125 3 1 10k A (SEE NOTE 2) B NOTES: 1. Monitor mode entry method: 10 k SW2: Position C -- High voltage entry (VTST); must use external OSC Bus clock depends on SW1 (note 2). SW2: Position D -- Reset vector must be blank ($FFFE:$FFFF = $FF) Bus clock = 1.2288MHz. 2. Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A -- Bus clock = OSC1 / 4 SW1: Position B -- Bus clock = OSC1 / 2 5. See Table 19-4. DC Electrical Characteristics for VTST voltage level requirements. SW1 10k PTA1 PTC1 PTA2 10 k V- 6 + 1 F 74HC125 5 6 4 VDD 10 k C1+ VCC 16 + 15 + 2 VTST VDD 1k 8.5 V D 10k PTA0 VDD VDD 1 F 1 F XTAL CIRCUIT C SW2 (SEE NOTE 1) IRQ VDD 6-30 pF 1M OSC2 0.22 F 10 nF VSS CGMXFC
OSC1
C1- C2+
GND V+
Figure 7-1. Monitor Mode Circuit
MC68HC908JW32 Data Sheet, Rev. 5 92 Freescale Semiconductor
Functional Description
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. IRQ = VTST (PLL off): - The external clock is 4.9152 MHz with PTC1 low 2. IRQ = VTST (PLL off): - The external clock is 9.8304 MHz with PTC1 high If VTST is applied to IRQ and PTC1 is low upon monitor mode entry (above condition set 1), the bus frequency is a divide-by-two of the input clock. If PTC1 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC1 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage is either VDD or VSS), then all port A pin requirements and conditions, including the PTC1 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Table 7-1. Monitor Mode Signal Requirements and Options
IRQ RST PTA2 PTA1 PTA0
(1)
PTC1
External Clock(2) X
Bus Freq. 0
PLL
COP
Baud Rate 0
Comment No operation until reset goes high PTA1 and PTA2 voltages only required if IRQ = VTST; PTC1 determines frequency divider PTA1 and PTA2 voltages only required if IRQ = VTST; PTC1 determines frequency divider
X
GND
X
X
X
X
X
Disabled
VTST
(3)
VDD or VTST
0
1
1
0
4.9152 MHz
2.4576 MHz
OFF
Disabled
9600
VTST(
3)
VDD or VTST
0
1
1
1
9.8304 MHz
2.4576 MHz
OFF
Disabled
9600
VDD or GND
VDD or VTST
X
X
X
X
X
--
OFF
Enabled
--
Enters user mode
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication 2. External clock is derived by a 4.9152/9.8304 MHz off-chip oscillator 3. Monitor mode entry by IRQ = VTST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is bypassed.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 93
Monitor ROM (MON)
The COP module is disabled in monitor mode based on these conditions: * If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the COP is always disabled regardless of the state of IRQ or RST. * If monitor mode was entered with VTST on IRQ (condition set 1), then the COP is disabled as long as VTST is applied to either IRQ or RST. The second condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. Enter monitor mode with pin configuration shown in Figure 7-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change (except for PTA1, where it should be held until after security, see 7.4 Security). Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. Table 7-2 summarizes the differences between user mode and monitor mode vectors. Table 7-2. Mode Differences (Vectors)
Functions Modes Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
User Monitor
7.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
START BIT NEXT START STOP BIT BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 7-2. Monitor Data Format
MC68HC908JW32 Data Sheet, Rev. 5 94 Freescale Semiconductor
Functional Description
7.3.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 7-3. Break Transaction
7.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTB0 pin (when IRQ1 is set to VTST) upon entry into monitor mode. When PTB0 is high, the divide by ratio is 1024. If the PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512. If monitor mode was entered with VDD on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0. This condition for monitor mode entry requires that the reset vector is blank. Table 7-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other standard baud rates can be accomplished using proportionally higher or lower frequency generators. If using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. Table 7-3. Monitor Baud Rate Selection
External Frequency 4.9152 MHz 9.8304 MHz 9.8304 MHz IRQ1 VTST VTST VDD PTB0 0 1 X Internal Frequency 2.4576 MHz 2.4576 MHz 2.4576 MHz Baud Rate (BPS) 9600 9600 9600
7.3.5 Commands
The monitor ROM firmware uses these commands: * READ (read memory) * WRITE (write memory) * IREAD (indexed read) * IWRITE (indexed write) * READSP (read stack pointer) * RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 95
Monitor ROM (MON)
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte.
FROM HOST
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
4 ECHO
1
4
1
4
1
3, 2
4 RETURN
Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte.
Figure 7-4. Read Transaction
FROM HOST
WRITE 3 ECHO 1
WRITE 3
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
1
3
1
3
1
2, 3
Notes: 1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte.
Figure 7-5. Write Transaction A brief description of each monitor mode command is given in Table 7-4 through Table 7-9. Table 7-4. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
ECHO
RETURN
MC68HC908JW32 Data Sheet, Rev. 5 96 Freescale Semiconductor
Functional Description
Table 7-5. WRITE (Write Memory) Command
Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence
FROM HOST
WRITE
WRITE
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 7-6. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 97
Monitor ROM (MON)
Table 7-7. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence
FROM HOST
IWRITE
IWRITE
DATA
DATA
ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 7-8. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence
FROM HOST
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
MC68HC908JW32 Data Sheet, Rev. 5 98 Freescale Semiconductor
Security
Table 7-9. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes PULH and RTI instructions None None $28 Command Sequence
FROM HOST
RUN
RUN
ECHO
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER SP + 1 SP + 2 SP + 3 SP + 4
HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7
Figure 7-6. Stack Pointer at Monitor Mode Entry
7.4 Security
A security feature discourages unauthorized reading of ROM locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data. NOTE Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 99
Monitor ROM (MON)
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all ROM locations and execute code from ROM. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 7-7.)
VDD 4096 + 32 CGMXCLK CYCLES RST COMMAND 2 BYTE 8 ECHO 4 1 COMMAND ECHO BREAK 256 BUS CYCLES (MINIMUM) BYTE 1 BYTE 2 BYTE 8 1 BYTE 2 ECHO 1
FROM HOST
PTA0 1 BYTE 1 ECHO FROM MCU 4
NOTES: 1 = Echo delay, 2 bit times. 2 = Data return delay, 2 bit times. 4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a ROM location returns an invalid value and trying to execute code from ROM causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bits. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is set. If it is, then the correct security code has been entered and ROM can be accessed.
MC68HC908JW32 Data Sheet, Rev. 5 100 Freescale Semiconductor
ROM-Resident Routines
7.5 ROM-Resident Routines
Five routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory manipulation. They are intended to simplify FLASH program, erase and load operations. Table 7-10 shows a summary of the ROM-resident routines. Table 7-10. Summary of ROM-Resident Routines
Routine Name PRGRNGE ERARNGE LDRNGE MON_PRGRNGE MON_ERARNGE Routine Description Program a range of locations Erase a page or the entire array Loads data from a range of locations Program a range of locations in monitor mode Erase a page or the entire array in monitor mode Call Address $FE10 $FE13 $FA31 $FF24 $FF28 Stack Used (bytes) 16 10 10 18 12
The routines are designed to be called as stand-alone subroutines in the user program or monitor mode. The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM. The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used, any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in Figure 7-8.
FILE_PTR $XXXX ADDRESS AS POINTER
R
A
M
BUS SPEED (BUS_SPD) DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA 1 DATA BLOCK
DATA ARRAY DATA N
Figure 7-8. Data Block Format for ROM-Resident Routines During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 101
Monitor ROM (MON)
The control and data bytes are described below. * Bus speed -- This one byte indicates the operating bus speed of the MCU. The value of this byte should be equal to 4 times the bus speed. E.g. for a 4MHz bus, the value is 16 ($10). This control byte is useful where the MCU clock source is switched between the PLL clock and the crystal clock. * Data size -- This one byte indicates the number of bytes in the data array that are to be manipulated. The maximum data array size is 255. Routines ERARNGE and MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning. * Start address -- These two bytes, high byte followed by low byte, indicate the start address of the FLASH memory to be manipulated. * Data array -- This data array contains data that are to be manipulated. Data in this array are programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE. For the read routines: LDRNGE and data is read from FLASH and stored in this array.
7.5.1 PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 7-11. PRGRNGE Routine
Routine Name Routine Description Calling Address Stack Used PRGRNGE Program a range of locations $FE10 16 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN)
Data Block Format
The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be programmed in one routine call is 255 bytes (max. DATASIZE is 255). ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment during programming. A check to see that all bytes in the specified range are erased is not performed by this routine prior programming. Nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. User must assure that the range specified is first erased. The coding example below is to program 64 bytes of data starting at FLASH location $EE00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block.
MC68HC908JW32 Data Sheet, Rev. 5 102 Freescale Semiconductor
ROM-Resident Routines
ORG : FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY PRGRNGE FLASH_START
RAM
DS.B DS.B DS.W DS.B EQU EQU
1 1 1 64 $FE10 $EE00
; ; ; ;
Indicates 4x bus frequency Data size to be programmed FLASH start address Reserved data array
ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE
7.5.2 ERARNGE
ERARNGE is used to erase a range of locations in FLASH. Table 7-12. ERARNGE Routine
Routine Name Routine Description Calling Address Stack Used ERARNGE Erase a page or the entire array $FE13 10 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL)
Data Block Format
There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (512 consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass erase. The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not used.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 103
Monitor ROM (MON)
The coding example below is to perform a page erase, from $EE00-$EFFF. The Initialization subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
ERARNGE MAIN: BSR : : LDHX JSR : EQU $FE13
INITIALISATION
#FILE_PTR ERARNGE
7.5.3 LDRNGE
LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 7-13. LDRNGE Routine
Routine Name Routine Description Calling Address Stack Used LDRNGE Loads data from a range of locations $FA31 10 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N
Data Block Format
The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be retrieved in one routine call is 255 bytes. The data retrieved from FLASH is loaded into the data array in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from FLASH that was previously programmed. The coding example below is to retrieve 64 bytes of data starting from $EE00 in FLASH. The Initialization subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
LDRNGE MAIN: BSR : : LDHX JSR : EQU $FA31
INITIALIZATION
#FILE_PTR LDRNGE
MC68HC908JW32 Data Sheet, Rev. 5 104 Freescale Semiconductor
Chapter 8 Timer Interface Module (TIM)
8.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 8-1 is a block diagram of the TIM. This particular MCU has a single timer interface modules which are denoted as TIM1.
8.2 Features
Features of the TIM include: * One input capture/output compare channel: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * Buffered and unbuffered pulse-width-modulation (PWM) signal generation * Programmable TIM clock input - with 7-frequency internal bus clock prescaler selection - External TIM clock input (bus frequency / 2 maximum) * Free-running or modulo up-count operation * Toggle channel pin on overflow * TIM counter stop and reset bits * Modular architecture expandable to eight channels
8.3 Pin Name Conventions
The text that follows describes the timer, TIM1. The TIM input/output (I/O) pin names are T1CH01 (timer channel 01). The TIMER shares three I/O pins with three port C I/O port pins. The timer clock input is used by TIM1 modules. The full names of the TIM I/O pins are listed in Table 8-1. The generic pin names appear in the text that follows. Table 8-1. Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: T1CH0 PTC0/T1CH0 T1CH1 PTC2/T1CH1 TCLK1 PTC1/TCLK1
NOTE References to timer 1 may be made in the following text by omitting the timer number. For example, TCH01 may refer generically to T1CH01.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 105
Timer Interface Module (TIM)
8.4 Functional Description
Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The TIM channel (per timer) is programmable independently as input capture or output compare channel. If a channel is configured as input capture, then an internal pullup device may be enabled for that channel. (See Chapter 13 Input/Output (I/O) Ports.)
TCLK1 PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS0A CH1F CH01IE CH1IE INTERRUPT LOGIC ELS0B ELS0A CH1MAX PORT LOGIC T1CH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC T1CH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 8-1. TIM Block Diagram Figure 8-2 summarizes the timer registers. NOTE References to timer 1 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC.
MC68HC908JW32 Data Sheet, Rev. 5 106 Freescale Semiconductor
Functional Description
Addr. $000A
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
Register Name Timer 1 Status and Control Read: Register Write: (T1SC) Reset: Timer 1 Counter Read: Register High Write: (T1CNTH) Reset: Timer 1 Counter Read: Register Low Write: (T1CNTL) Reset: Timer 1 Counter Modulo Read: Register High Write: (T1MODH) Reset: Timer 1 Counter Modulo Read: Register Low Write: (T1MODL) Reset: Read: Timer 1 Channel 0 Status and Write: Control Register (T1SC0) Reset: Timer 1 Channel 0 Read: Register High Write: (T1CH0H) Reset: Timer 1 Channel 0 Read: Register Low Write: (T1CH0L) Reset: Read: Timer 1 Channel 1 Status and Write: Control Register (T1SC1) Reset: Timer 1 Channel 1 Read: Register High Write: (T1CH1H) Reset: Timer 1 Channel 1 Read: Register Low Write: (T1CH1L) Reset:
Bit 7 TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15
6 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14
5 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13
4 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12
3 0 0 11 0 3 0 11 1 3 1 ELS0B 0 11
2 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10
1 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9
Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
Indeterminate after reset Bit 7 CH1F 0 0 Bit 15 6 5 0 0 13 4 3 2 1 Bit 0
Indeterminate after reset CH1IE 0 14 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Indeterminate after reset Bit 7 6 = Unimplemented 5 4 3 2 1 Bit 0
Indeterminate after reset
Figure 8-2. TIM I/O Register Summary
8.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source.
8.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 107
Timer Interface Module (TIM)
8.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 8.4.3.1 Unbuffered Output Compare Output compare channel 0 can generate unbuffered output compare pulses as described in 8.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel 0: * When changing to a smaller value, enable channel 0 output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. * When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 8.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
MC68HC908JW32 Data Sheet, Rev. 5 108 Freescale Semiconductor
Functional Description
8.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 8-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 8.9.1 TIM Status and Control Register.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 8-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 8.4.4.1 Unbuffered PWM Signal Generation Output compare channel 0 can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel 0:
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 109
Timer Interface Module (TIM)
*
*
When changing to a shorter pulse width, enable channel 0 output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
8.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 8.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
MC68HC908JW32 Data Sheet, Rev. 5 110 Freescale Semiconductor
Interrupts
4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 8-3.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 8.9.4 TIM Channel Status and Control Registers.)
8.5 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. * TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
8.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
8.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 111
Timer Interface Module (TIM)
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
8.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
8.7 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 6.7.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
8.8 I/O Signals
Port C shares three of its pins with the TIM. The two TIM channel I/O pins are PTC0/T1CH0 and PTC2/T1CH1; and the external clock input is PTC1/TCLK1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 can be configured as buffered output compare or buffered PWM pins.
8.8.1 TIM Clock Pin (PTC1/TCLK1)
PTC1/TCLK1 is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock. Select the PTC1/TCLK1 input by writing logic 1's to the three prescaler select bits, PS[2:0]. (See 8.9.1 TIM Status and Control Register.) The minimum T2CLK pulse width, TCLK1LMIN or TCLK1HMIN, is:
1 ------------------------------------ + t SU bus frequency
The maximum TCLK1 frequency is: bus frequency / 2
8.9 I/O Registers
NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC.
MC68HC908JW32 Data Sheet, Rev. 5 112 Freescale Semiconductor
I/O Registers
These I/O registers control and monitor operation of the TIM: * TIM status and control register (TSC) * TIM counter registers (TCNTH:TCNTL) * TIM counter modulo registers (TMODH:TMODL) * TIM channel status and control registers (TSC0, TSC1) * TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
8.9.1 TIM Status and Control Register
The TIM status and control register (TSC): * Enables TIM overflow interrupts * Flags TIM overflows * Stops the TIM counter * Resets the TIM counter * Prescales the TIM counter clock
Address: $000A Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
= Unimplemented
Figure 8-4. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 113
Timer Interface Module (TIM)
TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 8-2 shows. Reset clears the PS[2:0] bits. Table 8-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 TCLK1
8.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: $000C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Figure 8-5. TIM Counter Registers High (TCNTH)
MC68HC908JW32 Data Sheet, Rev. 5 114 Freescale Semiconductor
I/O Registers Address: $000D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Figure 8-6. TIM Counter Registers Low (TCNTL)
8.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $000E Bit 7 Read: Write: Reset: Bit 15 1 6 14 1 5 13 1 4 12 1 3 11 1 2 10 1 1 9 1 Bit 0 Bit 8 1
Figure 8-7. TIM Counter Modulo Register High (TMODH)
Address: $000F Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1
Figure 8-8. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers.
8.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers: * Flags input captures and output compares * Enables input capture and output compare interrupts * Selects input capture, output compare, or PWM operation * Selects high, low, or toggling output on output compare * Selects rising edge, falling edge, or any edge as the active input capture trigger * Selects output toggling on TIM overflow * Selects 0% and 100% PWM duty cycle * Selects buffered or unbuffered output compare/PWM operation
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 115
Timer Interface Module (TIM)
Address: $0010 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Figure 8-9. TIM Channel 0 Status and Control Register (TSC0)
Address: $0013 Bit 7 Read: Write: Reset: CH1F 0 0 6 CH1IE 0 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0
= Unimplemented
Figure 8-10. TIM Channel 1 Status and Control Register (TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 8-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation
MC68HC908JW32 Data Sheet, Rev. 5 116 Freescale Semiconductor
I/O Registers
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 8-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 8-3. Mode, Edge, and Level Selection
MSxB:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X ELSxB:ELSxA 00 Output preset 00 01 10 11 01 10 11 01 10 11 Buffered output compare or buffered PWM Output compare or PWM Input capture Mode Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare
NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 117
Timer Interface Module (TIM)
CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 8-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 8-11. CHxMAX Latency
8.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0011 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 8-12. TIM Channel 0 Register High (TCH0H)
Address: $0012 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 8-13. TIM Channel 0 Register Low (TCH0L)
MC68HC908JW32 Data Sheet, Rev. 5 118 Freescale Semiconductor
I/O Registers Address: $0014 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 8-14. TIM Channel 1 Register High (TCH1H)
Address: $0015 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 8-15. TIM Channel 1 Register Low (TCH1L)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 119
Timer Interface Module (TIM)
MC68HC908JW32 Data Sheet, Rev. 5 120 Freescale Semiconductor
Chapter 9 Timebase Module (TBM)
9.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the selected OSCCLK clock from the oscillator module. This TBM version uses 18 divider stages, eight of which are user selectable.
9.2 Features
Features of the TBM module include: * 88-kHz build-in RC clock. * Software programmable ~3s, ~1.5s, ~745ms, ~372ms, ~186ms, ~93ms, ~47ms, and ~23ms periodic interrupt * User selectable oscillator clock source enable during stop mode to allow periodic wake-up from stop
9.3 Functional Description
This module can generate a periodic interrupt by dividing the oscillator clock frequency, OSCCLK. The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 9-1, starts counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 121
Timebase Module (TBM)
TBON
/2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2
/2
/ 2048
/2
/ 4096
/2
/ 8192
/2
/ 16384 / 32768
88-kHz Internal RC OSC
TBR0
TBR2
TBR1
/2
/2
/ 65536
/2
/ 131072 / 262144
TBMINT
000 001 010 011 100 101 110 111 SEL
R TBIF TBIE
Figure 9-1. Timebase Block Diagram
9.4 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate.
Address: Read: Write: Reset: 0 $0018 Bit 7 TBIF 6 TBR2 0 5 TBR1 0 4 TBR0 0 3 0 TACK 0 R 2 TBIE 0 = Reserved 1 TBON 0 Bit 0 R 0
= Unimplemented
Figure 9-2. Timebase Control Register (TBCR) TBIF -- Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending
MC68HC908JW32 Data Sheet, Rev. 5 122 Freescale Semiconductor
TACK
Interrupts
TBR2-TBR0 -- Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 9-1. Table 9-1. Timebase Rate Selection (88-kHz Reference)
Timebase Interrupt Rate TBR2 0 0 0 0 1 1 1 1 TBR1 0 0 1 1 0 0 1 1 TBR0 0 1 0 1 0 1 0 1 Divider Hz 262144 131072 65536 32768 16384 8192 4096 2048 ~0.33 ~0.67 ~1.3 ~2.7 ~5.4 ~10.7 ~21.5 ~43.0 ms ~2979 ~1489 ~745 ~372 ~186 ~93 ~47 ~23
NOTE Do not change TBR2-TBR0 bits while the timebase is enabled (TBON = 1). TACK -- Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect TBIE -- Timebase Interrupt Enabled This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit. 1 = Timebase interrupt enabled 0 = Timebase interrupt disabled TBON -- Timebase Enabled This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit. 1 = Timebase enabled 0 = Timebase disabled and the counter initialized to 0s
9.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2-TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. The interrupt vector is defined in Table 6-3. Interrupt Sources. Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 123
Timebase Module (TBM)
9.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
9.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction.
9.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the stop mode oscillator enable bit (STOP_RCLKEN) for the selected oscillator in the CONFIG2 register. The timebase module can be used in this mode to generate a periodic walk-up from stop mode. If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during STOP mode. In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction.
MC68HC908JW32 Data Sheet, Rev. 5 124 Freescale Semiconductor
Chapter 10 Serial Peripheral Interface Module (SPI)
10.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices.
10.2 Features
Features of the SPI module include the following: * Full-duplex operation * Master and slave modes * Double-buffered operation with separate transmit and receive registers * Four master mode frequencies (maximum = bus frequency / 2) * Maximum slave mode frequency = bus frequency * Serial clock with programmable polarity and phase * Two separately enabled interrupts: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) * Mode fault error flag with CPU interrupt capability * Overflow error flag with CPU interrupt capability * Programmable wired-OR mode
10.3 Pin Name Conventions and I/O Register Addresses
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 10-1. The generic pin names appear in the text that follows. Table 10-1. Pin Name Conventions
SPI Generic Pin Names: Full SPI Pin Names: SPI MISO PTE6/MISO MOSI PTE5/MOSI SS PTE7/SS SPSCK PTE4/SPSCK CGND VSS
Figure 10-1 summarizes the SPI I/O registers.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 125
Serial Peripheral Interface Module (SPI)
Addr.
Register Name Read:
Bit 7 SPRIE 0 SPRF 0 R7 T7
6 R 0 ERRIE 0 R6 T6
5 SPMSTR 1 OVRF 0 R5 T5
4 CPOL 0 MODF 0 R4 T4
3 CPHA 1 SPTE 1 R3 T3 R
2 SPWOM 0 MODFEN 0 R2 T2 = Reserved
1 SPE 0 SPR1 0 R1 T1
Bit 0 SPTIE 0 SPR0 0 R0 T0
$004C SPI Control Register (SPCR) Write: Reset: $004D SPI Status and Control Read: Register Write: (SPSCR) Reset: Read: SPI Data Register Write: (SPDR) Reset:
$004E
Unaffected by reset = Unimplemented
Figure 10-1. SPI I/O Register Summary
10.4 Functional Description
Figure 10-2 shows the structure of the SPI module. The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt-driven. The following paragraphs describe the operation of the SPI module.
10.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 10.13.1 SPI Control Register.) Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. (See Figure 10-3.) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 10.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit.
MC68HC908JW32 Data Sheet, Rev. 5 126 Freescale Semiconductor
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER CGMOUT / 2 FROM SIM 7 /2 /8 CLOCK DIVIDER / 32 / 128 CLOCK SELECT MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS 6
SHIFT REGISTER 5 4 3 2 1 0 MISO
SPMSTR
SPE
SPR1
SPR0
SPMSTR
CPHA
CPOL
RESERVED TRANSMITTER CPU INTERRUPT REQUEST RESERVED RECEIVER/ERROR CPU INTERRUPT REQUEST SPI CONTROL
MODFEN ERRIE SPTIE SPRIE R SPE SPRF SPTE OVRF MODF
SPWOM
Figure 10-2. SPI Module Block Diagram
MASTER MCU SLAVE MCU
SHIFT REGISTER
MISO MOSI SPSCK
MISO MOSI SPSCK SS
SHIFT REGISTER
BAUD RATE GENERATOR
SS
VDD
Figure 10-3. Full-Duplex Master-Slave Connections
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 127
Serial Peripheral Interface Module (SPI)
10.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. (See 10.7.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See 10.5 Transmission Formats.) NOTE SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge.
10.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiple-master bus contention.
10.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE).
MC68HC908JW32 Data Sheet, Rev. 5 128 Freescale Semiconductor
Transmission Formats
10.5.2 Transmission Format When CPHA = 0
Figure 10-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 10.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave's SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 10-5.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB 1 2 3 4 5 6 7 8
Figure 10-4. Transmission Format (CPHA = 0)
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3
Figure 10-5. CPHA/SS Timing When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 129
Serial Peripheral Interface Module (SPI)
10.5.3 Transmission Format When CPHA = 1
Figure 10-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 10.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB 1 2 3 4 5 6 7 8
Figure 10-6. Transmission Format (CPHA = 1) When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission.
10.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 10-7.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 10-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
MC68HC908JW32 Data Sheet, Rev. 5 130 Freescale Semiconductor
Queuing Transmission Data
WRITE TO SPDR BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK / 128; 128 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 2; 2 POSSIBLE START POINTS
Figure 10-7. Transmission Start Delay (Master)
10.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 10-8 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 131
Serial Peripheral Interface Module (SPI)
WRITE TO SPDR SPTE SPSCK CPHA:CPOL = 1:0 MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654 654321 654321 BYTE 1 BYTE 2 BYTE 3 4 6 7 7 CPU READS SPDR, CLEARING SPRF BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 9 11 12 1 2 3 5 8 10
SPRF READ SPSCR READ SPDR 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET.
Figure 10-8. SPRF/SPTE CPU Interrupt Timing The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur.
10.7 Error Conditions
The following flags signal SPI error conditions: * Overflow (OVRF) -- Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. * Mode fault error (MODF) -- The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
MC68HC908JW32 Data Sheet, Rev. 5 132 Freescale Semiconductor
Error Conditions
10.7.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7. (See Figure 10-4 and Figure 10-6.) If an overflow occurs, all data received after the overflow and before the OVRF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive data register before the overflow occurred can still be read. Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 10-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 10-9 shows how it is possible to miss an overflow. The first part of Figure 10-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR are read.
BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8
SPRF
OVRF READ SPSCR READ SPDR 1 2 3 4 2 5
3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8
7 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 10-9. Missed Read of Overflow Condition In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 10-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 133
Serial Peripheral Interface Module (SPI)
BYTE 1 SPI RECEIVE COMPLETE SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 5 6 7 2 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 4 6 8 8 9 9 10 12 13 14 1 BYTE 2 5 BYTE 3 7 BYTE 4 11
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 10-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
10.7.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: * The SS pin of a slave SPI goes high during a transmission * The SS pin of a master SPI goes low at any time For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 10-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: * If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. * The SPE bit is cleared. * The SPTE bit is set. * The SPI state counter is cleared. * The data direction register of the shared I/O port regains control of port drivers.
MC68HC908JW32 Data Sheet, Rev. 5 134 Freescale Semiconductor
Interrupts
NOTE To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit. (See 10.5 Transmission Formats.) NOTE Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave. When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
10.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. Table 10-2. SPI Interrupts
Flag SPTE Transmitter empty SPRF Receiver full OVRF Overflow MODF Mode fault Request SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request (SPRIE = 1) SPI receiver/error interrupt request (ERRIE = 1) SPI receiver/error interrupt request (ERRIE = 1)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 135
Serial Peripheral Interface Module (SPI)
Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, regardless of the state of the SPE bit. (See Figure 10-11.) The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
NOT AVAILABLE
SPTE
SPTIE
SPE SPI TRANSMITTER CPU INTERRUPT REQUEST
R
NOT AVAILABLE
SPRIE
SPRF
SPI RECEIVER/ERROR ERRIE MODF OVRF CPU INTERRUPT REQUEST
Figure 10-11. SPI Interrupt Request Generation The following sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. * SPI transmitter empty (SPTE) -- The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request.
MC68HC908JW32 Data Sheet, Rev. 5 136 Freescale Semiconductor
Resetting the SPI
10.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: * The SPTE flag is set. * Any transmission currently in progress is aborted. * The shift register is cleared. * The SPI state counter is cleared, making it ready for a new complete transmission. * All the SPI port logic is defaulted back to being general-purpose I/O. These items are reset only by a system reset: * All control bits in the SPCR register * All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) * The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
10.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
10.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). (See 10.8 Interrupts.)
10.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
10.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Chapter 6 System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 137
Serial Peripheral Interface Module (SPI)
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
10.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are: * MISO -- Data received * MOSI -- Data transmitted * SPSCK -- Serial clock * SS -- Slave select * CGND -- Clock ground (internally connected to VSS) The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD.
10.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port.
10.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port.
10.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
MC68HC908JW32 Data Sheet, Rev. 5 138 Freescale Semiconductor
I/O Signals
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port.
10.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 10.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Figure 10-12.
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3
Figure 10-12. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. (See 10.13.2 SPI Status and Control Register.) NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 10.7.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. (See Table 10-3.) Table 10-3. SPI Configuration
SPE 0 1 1 1 SPMSTR X(1) 0 1 1 MODFEN X X 0 1 SPI Configuration Not enabled Slave Master without MODF Master with MODF State of SS Logic General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI
Note 1. X = Don't care
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 139
Serial Peripheral Interface Module (SPI)
10.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to VSS as shown in Table 10-1.
10.13 I/O Registers
Three registers control and monitor SPI operation: * SPI control register (SPCR) * SPI status and control register (SPSCR) * SPI data register (SPDR)
10.13.1 SPI Control Register
The SPI control register: * Enables SPI module interrupt requests * Configures the SPI module as master or slave * Selects serial clock polarity and phase * Configures the SPSCK, MOSI, and MISO pins as open-drain outputs * Enables the SPI module
Address: Read: Write: Reset: $004C Bit 7 SPRIE 0 R 6 R 0 = Reserved 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 1 SPE 0 Bit 0 SPTIE 0
Figure 10-13. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR -- SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 10-4 and Figure 10-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA -- Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 10-4 and Figure 10-6.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 10-12.) Reset sets the CPHA bit.
MC68HC908JW32 Data Sheet, Rev. 5 140 Freescale Semiconductor
I/O Registers
SPWOM -- SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 10.9 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled
10.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions: * Receive data register full * Failure to clear SPRF bit before next byte is received (overflow error) * Inconsistent logic level on SS pin (mode fault error) * Transmit data register empty The SPI status and control register also contains bits that perform these functions: * Enable error interrupts * Enable mode fault error detection * Select master SPI baud rate
Address Read: Write: Reset: 0 $004D Bit 7 SPRF 6 ERRIE 0 5 OVRF 0 4 MODF 0 3 SPTE 1 2 MODFEN 0 1 SPR1 0 Bit 0 SPR0 0
= Unimplemented
Figure 10-14. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 141
Serial Peripheral Interface Module (SPI)
ERRIE -- Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit. 1 = Overflow 0 = No overflow MODF -- Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also. NOTE Do not write to the SPI data register unless the SPTE bit is high. During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN -- Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See 10.12.4 SS (Slave Select).) If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See 10.7.2 Mode Fault Error.)
MC68HC908JW32 Data Sheet, Rev. 5 142 Freescale Semiconductor
I/O Registers
SPR1 and SPR0 -- SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 10-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 10-4. SPI Master Baud Rate Selection
SPR1 and SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128
Use this formula to calculate the SPI baud rate:
CGMOUT Baud rate = ------------------------2 x BD
where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor
10.13.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. (See Figure 10-2.)
Address: Read: Write: Reset: $004E Bit 7 R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Unaffected by reset
Figure 10-15. SPI Data Register (SPDR) R7-R0/T7-T0 -- Receive/Transmit Data Bits NOTE Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 143
Serial Peripheral Interface Module (SPI)
MC68HC908JW32 Data Sheet, Rev. 5 144 Freescale Semiconductor
Chapter 11 USB 2.0 FS Module
11.1 Introduction
This section describes the universal serial bus (USB) module. The USB module is designed to serve as a full speed (FS) USB device per the Universal Serial Bus Specification Rev 2.0. Control and interrupt data transfers are supported. Endpoint 0 functions as a transmit/receive control endpoint; endpoint 1, 2, 3 and 4 functions are configurable as interrupt or bulk endpoints and support transmit or receive communication.
11.2 Features
Features of the USB module include: * Full Universal Serial Bus Specification 2.0 full-speed functions * 12Mbps data rate * On-chip 3.3V regulator * Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer * 64 bytes programmable buffer to share with 4 data endpoint * 4 data endpoints supports * USB device controller with protocol control supports single configuration, 2 interfaces and no alternate settings for each interface * Programmable endpoint type for four independent endpoints -- interrupt or bulk * USB data control logic: - Packet identification and decoding/generation - CRC generation and checking - NRZI (Non-Return-to Zero Inserted) encoding/decoding - Bit-stuffing - Sync detection - End-of-packet detection * USB reset options: - Internal MCU reset generation - CPU interrupt request generation * Suspend and resume operations, with remote wakeup support
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 145
USB 2.0 FS Module
11.3 USB Module Architecture
3.3V Regulator
3.3V
USB Control Logic
USB Request Processor
D+
D-
USB Transceiver
Endpoint Buffer
USB Endpoint Controller
System Bus
Figure 11-1. USB Module Block Diagram The USB module block diagram is shown in Figure 11-1. The module involves six major blocks - USB transceiver, USB control logic, USB request processor, USB endpoint controller and USB Endpoint buffer.
11.3.1 USB Transceiver
The USB transceiver is electrically compliant to the Universal Serial Bus Specification 2.0. The on-chip 3.3V regulator provides a stable power source for the termination pull-up resistor. Full speed devices are terminated with the pull-up resistor on the D+ line.
MC68HC908JW32 Data Sheet, Rev. 5 146 Freescale Semiconductor
USB Module Architecture
11.3.2 USB Control Logic
The USB control logic handle the following functions: * For transmit data - Packet creation - CRC generation - NRZI encoding - Bit stuffing * For receive data - Sync detection - Packet Identification - End-of-packet (EOP) detection - CRC validation - NRZI decoding - Bit unstuffing * For error detection - Bad CRC - Timeout detection for EOP - Bit stuffing violation
11.3.3 USB Endpoint Configuration
A single configuration and 2 interfaces are supported by the module. Endpoint 0 is always used as control endpoint. The interface number for endpoint 1 to 4 are programmable through USB interface control register (UINTFCR). The endpoint type and direction of all endpoint 1 to 4 is software programmable to either BULK or INTERRUPT and either IN or OUT respectively. The endpoint configuration is summarized in Table 11-1 Table 11-1. Endpoint Summary
Endpoint Number 0 1 2 3 4 Configuration Number -- 1 1 1 1 Interface Number -- EP1INT EP2INT EP3INT EP4INT Direction IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT Type Control Bulk/ Interrupt Bulk/ Interrupt Bulk/ Interrupt Bulk/ Interrupt
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 147
USB 2.0 FS Module
11.3.4 USB Requestor Processor
The USB requestor processor automatically process some standard USB requests as listed in Table 11-2. Table 11-2. USB Requests Handling
Request Handling Requestor processor clears the feature specified by the feature selector. For USB specification 2.0, only two features are specified DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT. The module stores the HALT status and remote wakeup status internally. No user attention is required. Return the configuration number specified in CONFIG. No user notification is provided. This requests is not handled automatically by the request processor. User is notified by the SETUP flag and the TFRC_OUT flag being set. The request command can be decoded through the 8-byte endpoint 0 OUT data buffer. User must fill up the Endpoint 0 data IN buffer 8 bytes at a time manually with the corresponding descriptor requested by the host. When DVALID_IN bit is set and TFRC_IN flag is cleared, the requestor processor responses to the next IN packet with the data stored. Before the DVALID_IN bit is set, NAK is returned to all IN packet. No alternate setting is support by the module, Alternative interface number zero is always return. No user notification is provided. Returns the current status of the specified device, endpoint or interface. No user notification is provided. Internal address register is modified. The control logic begins responding to the new address once the status stage of the request completes successfully. No user notification is provided. If the configuration value is zero, the USB module is placed into the unconfigured state. If the device is successfully configured by the host, the new configuration value is specified by CONFIG bit. SET_CONFIGURATION NOTE: User is notified if the request completes successfully. CONFIG_CHG flag of USB Status Register (USBSR) will be set upon a successful completion of the request where the configuration number is changed from zero to one. User can read the CONFIG flag for the corresponding changes. Not supported. STALL packet is returned to the host. Corresponding feature specified by the packet is enabled accordingly. No user attention is required. No alternative setting is supported. If the alternative setting number is zero, ACK is returned to the host. No user notification is provided. Passed to the user as a vendor specific request. SYNC_FRAME NOTE: SETUP flag, TFRC_OUT flag and DVALID_OUT flag will be set. User should decode the request via reading the endpoint 0 data registers (UE0D0-UE0D7).
CLEAR_FEATURE
GET_CONFIGURATION
GET_DESCRIPTOR
GET_INTERFACE GET_STATUS
SET_ADDRESS
SET_DESCRIPTOR SET_FEATURE SET_INTERFACE
MC68HC908JW32 Data Sheet, Rev. 5 148 Freescale Semiconductor
USB Module Architecture
11.3.4.1 Configuration Process All USB devices must be configured before used. The host will configure the device according to the configuration process defined by the USB specification 2.0 Chapter 9. During the process most of the USB commands issued by the host are responded automatically except GET_DESCRIPTOR, SYNC_FRAME, vendor specific and class specific commands where user interaction is required. These are known as the user commands. The number of configurations and interfaces supported is limited by the module. This module can support a single configuration and maximum of two interfaces. No alternate setting is allowed. Upon the reception of the user commands, no module level decoding is done instead user is notified by the SETUP flag and TFRC_OUT flag. User can then decode the command through the dedicated 8-byte endpoint 0 buffer. For instance, when a valid GET_DESCRIPTOR command is detected, user is notified by the SETUP, TFRC_OUT flag and DVALID_OUT flag. User should decode the command via the 8-byte endpoint 0 OUT buffer. Corresponding return descriptor is written to the endpoint 0 IN buffer 8 bytes at a time. By setting the DVALID_IN bit, the data is sent to the host in the next IN packet. Otherwise, the module will return NAK to all IN packet. If ACK is not returned from the host, the data is re-sent automatically in the next IN packet until ACK is returned from the host, then transfer complete flag TFRC_IN is set, the next 8 bytes of data can be written to the endpoint 0 IN buffer. The process continues until the requested descriptor is sent completely. NOTE Please note the module will return ACK to all valid SETUP packet. No software attention is required. Endpoint 0 buffer and endpoint 0 data size register (DSIZE) will be updated on every incoming SETUP packet. However, SETUP or TFRC_OUT will not be set unless the SETUP packet is a valid GET_DESCRIPTOR, SYNC_FRAME or class/vendor specific SETUP command. 11.3.4.2 Control Endpoint 0 Endpoint 0 is always treated as control endpoint. It has eight bytes dedicated buffer for device transmit (IN packet) and eight bytes dedicated buffer for device receive (OUT packet). Most of the host requests is handled by the requestor processor excepts the class/vendor specified request, GET_DESCRIPTOR request and the SYNC_FRAME request. If the user is notified by the module about the arrival of such requests, user can decode the request command by reading the endpoint 0 data register. The SETUP flag will be set if the 8-byte setup packet is received without CRC/Token/EOP error for Vendor/Class/SetDescriptor/SynchFrame commands only. NOTE For any OUT data received in the 8-byte endpoint OUT buffer, they are only valid until the start of any SETUP packet addressed to the device, even if the packet is corrupted the 8-byte OUT buffer may still be overwritten by this new SETUP packet. There is no indication of the corruption built into this module.
11.3.5 Endpoint Controller
The module has four independent endpoint controllers that managed the data transfer between CPU and the USB host. Each of these endpoint can be configured to either one of the two modes - bulk or interrupt.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 149
USB 2.0 FS Module
There are 64-byte RAM buffer to share between the four data endpoints. User is required to specify the buffer base address and the buffer size for each endpoint used. The buffer is separated in 8 bytes page, therefore, there are 8 pages in total. For example, if 16 bytes of buffer is required for endpoint 1 and 16 bytes is required for endpoint 2, the buffer base address for endpoint 1 can be specified as %000, while the buffer base address for endpoint 2 can be specified %010 and the buffer size SIZE[1:0] register should be defined as %01 and %01 respectively. 11.3.5.1 OUT endpoint Data Transfer The buffer size assigned to the endpoint is required to match with the endpoint definition specified in the endpoint descriptor. On every packet of data transfer, data loaded to the endpoint buffers are started with the buffer base address. If the data is valid, the complete packet is downloaded to the buffer RAM and ACK is sent automatically. The packet size is reported to DSIZE register and the transfer complete flag (TFRC) is set. User should wait until the data valid bit (DVALID) to be set before reading the data from the buffers. Otherwise, if CRC error encountered, the data packet is ignored and no handshake is returned. 11.3.5.2 IN endpoint Data Transfer When IN packet is received by the module and DVALID bit is cleared, NAK is returned. If the IN packet is corresponding to endpoint 0, user is required to write data to the dedicate 8 bytes registers, then DSIZE should be updated before setting DVALID bit to send data via the next IN packet. If the IN packet is corresponding to other endpoint 1 to 4, user is required to write data to corresponding endpoint buffer indicated by the BASE pointer. When the packet is transmitted successfully that ACK is returned from the host, DVALID bit is returned to zero. Transfer complete flag (TFRC) is set to notify user for the next transfer.
11.4 Interrupt Source
There are two interrupt source reserved for the USB module. Table 11-3. Interrupt Source Table
Flag TFRC0_IN TFRC0_OUT TFRC1 TFRC2 TFRC3 TFRC4 SETUP SOF CONFIG_CHG USBRST RESUMEF SUSPND Interrupt Source USB Endpoint Interrupt USB Endpoint Interrupt USB Endpoint Interrupt USB Endpoint Interrupt USB Endpoint Interrupt USB Endpoint Interrupt USB System Interrupt USB System Interrupt USB System Interrupt USB System Interrupt USB System Interrupt USB System Interrupt
MC68HC908JW32 Data Sheet, Rev. 5 150 Freescale Semiconductor
USB Module Registers
11.5 USB Module Registers
Addr.
$0051
Register Name
Read: USB Control Register Write: (USBCR) Reset: Read: USB Status Register Write: (USBSR) Reset: USB Status Interrupt Read: Mask Register Write: (USIMR) Reset:
Bit 7
USBEN 0 CONFIG 0 R 0 DSIZE3_ OUT
6
USBCLKEN 0
5
TFC4IE 0 SETUP
4
TFC3IE 0 SOF 0 SOFIE 0 DSIZE0_ OUT DSIZE0_IN 0 DIR 0 DIR 0 DIR 0 DIR 0 DSIZE4 0 DSIZE4 0 DSIZE4 0 DSIZE4 0
3
TFC2IE 0 CONFIG_ CHG 0 CONFIG_ CHGIE 0 DVALID_IN 0 SIZE1 0 SIZE1 0 SIZE1 0 SIZE1 0 DSIZE3 0 DSIZE3 0 DSIZE3 0 DSIZE3 0 R
2
TFC1IE 0 USBRST 0 USBRESETIE 0 TFRC_IN 0 SIZE0 0 SIZE0 0 SIZE0 0 SIZE0 0 DSIZE2 0 DSIZE2 0 DSIZE2 0 DSIZE2 0 = Reserved
1
TFC0IE 0 RESUMEF 0 RESUMEFIE 0 DVALID_ OUT 0 DVALID 0 DVALID 0 DVALID 0 DVALID 0 DSIZE1 0 DSIZE1 0 DSIZE1 0 DSIZE1 0
Bit 0
0 RESUME 0 SUSPND 0 SUSPNDIE 0 TFRC_OUT 0 TFRC 0 TFRC 0 TFRC 0 TFRC 0 DSIZE0 0 DSIZE0 0 DSIZE0 0 DSIZE0 0
$0052
0 0 EP0_STALL 0 DSIZE2_ OUT DSIZE2_IN 0 MODE0 0 MODE0 0 MODE0 0 MODE0 0 DSIZE6
0 SETUPIE 0 DSIZE1_ OUT DSIZE1_IN 0 0 STALL 0 0 STALL 0 0 STALL 0 0 STALL 0 DSIZE5 0 DSIZE5 0 DSIZE5 0 DSIZE5 0
$0053
$0054
USB EPO Read: Control/Status Write: DSIZE3_IN Register (UEP0CSR) Reset: 0 MODE1 0 MODE1 0 MODE1 0 MODE1 0
USB EP1 Read: $0055 Control/Status Write: Register (UEP1CSR) Reset: $0056 USB EP2 Read: Control/Status Write: Register (UEP2CSR) Reset: USB EP3 Read: Control/Status Write: Register (UEP3CSR) Reset: USB EP4 Read: Control/Status Write: Register (UEP4CSR) Reset: USB EP1 Data Size Read: Register Write: (UEP1DSR) Reset: USB EP2 Data Size Read: Register Write: (UEP2DSR) Reset: USB EP3 Data Size Read: Register Write: (UEP3DSR) Reset: USB EP4 Data Size Read: Register Write: (UEP4DSR) Reset:
$0057
$0058
$0059
0
0 DSIZE6
$005A
0
0 DSIZE6
$005B
0
0 DSIZE6
$005C
0
0
U = Unaffected by reset
Figure 11-2. USB Registers
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 151
USB 2.0 FS Module
Addr.
$005D
Register Name
USB EP 1/2 Base Read: Pointer Register Write: (UEP12BPR) Reset: USB EP 3/4 Base Read: Pointer Register Write: (UEP34BPR) Reset:
Bit 7
6
BASE22
5
BASE21 0 BASE41 0
4
BASE20 0 BASE40 0 EP3INT
3
2
BASE12
1
BASE11 0 BASE31 0
Bit 0
BASE10 0 BASE30 0 EP1INT
0
0 BASE42
0
0 BASE32
$005E
0
0 EP4INT
0
0 EP2INT
USB Interface Control Read: $005F Register Write: (UINTFCR) Reset:
0
0
0
0
0
0
0
0
UE0D07_ UE0D06_ UE0D05_ UE0D04_ UE0D03_ UE0D02_ UE0D01_ UE0D00_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0040 Register 0 Write: UE0D07_IN UE0D06_IN UE0D05_IN UE0D04_IN UE0D03_IN UE0D02_IN UE0D01_IN UE0D00_IN (UE0D0) Reset: Unaffected by reset UE0D17_ UE0D16_ UE0D15_ UE0D14_ UE0D13_ UE0D12_ UE0D11_ UE0D10_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0041 Register 1 Write: UE0D17_IN UE0D16_IN UE0D15_IN UE0D14_IN UE0D13_IN UE0D12_IN UE0D11_IN UE0D10_IN (UE0D1) Reset: Unaffected by reset UE0D27_ UE0D26_ UE0D25_ UE0D24_ UE0D23_ UE0D22_ UE0D21_ UE0D20_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0042 Register 2 Write: UE0D27_IN UE0D26_IN UE0D25_IN UE0D24_IN UE0D23_IN UE0D22_IN UE0D21_IN UE0D20_IN (UE0D2) Reset: Unaffected by reset UE0D37_ UE0D36_ UE0D35_ UE0D34_ UE0D33_ UE0D32_ UE0D31_ UE0D30_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0043 Register 3 Write: UE0D37_IN UE0D36_IN UE0D35_IN UE0D34_IN UE0D33_IN UE0D32_IN UE0D31_IN UE0D30_IN (UE0D3) Reset: Unaffected by reset UE0D47_ UE0D46_ UE0D45_ UE0D44_ UE0D43_ UE0D42_ UE0D41_ UE0D40_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0043 Register 4 Write: UE0D47_IN UE0D46_IN UE0D45_IN UE0D44_IN UE0D43_IN UE0D42_IN UE0D41_IN UE0D40_IN (UE0D4) Reset: Unaffected by reset UE0D57_ UE0D56_ UE0D55_ UE0D54_ UE0D53_ UE0D52_ UE0D51_ UE0D50_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0044 Register 5 Write: UE0D57_IN UE0D56_IN UE0D55_IN UE0D54_IN UE0D53_IN UE0D52_IN UE0D51_IN UE0D50_IN (UE0D5) Reset: Unaffected by reset UE0D67_ UE0D66_ UE0D65_ UE0D64_ UE0D63_ UE0D62_ UE0D61_ UE0D60_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0045 Register 6 Write: UE0D67_IN UE0D66_IN UE0D65_IN UE0D64_IN UE0D63_IN UE0D62_IN UE0D61_IN UE0D60_IN (UE0D6) Reset: Unaffected by reset UE0D77_ UE0D76_ UE0D75_ UE0D74_ UE0D73_ UE0D72_ UE0D71_ UE0D70_ USB Endpoint 0 Data Read: OUT OUT OUT OUT OUT OUT OUT OUT $0046 Register 7 Write: UE0D77_IN UE0D76_IN UE0D75_IN UE0D74_IN UE0D73_IN UE0D72_IN UE0D71_IN UE0D70_IN (UE0D7) Reset: Unaffected by reset U = Unaffected by reset R = Reserved
Figure 11-2. USB Registers (Continued)
MC68HC908JW32 Data Sheet, Rev. 5 152 Freescale Semiconductor
USB Module Registers
11.5.1 USB Control Register (USBCR)
Address: Read: Write: Reset: $0051 Bit 7 USBEN 0 6 USBCLKEN 0 5 TC4IE 0 4 TC3IE 0 3 TC2IE 0 2 TFC1IE 0 1 TC0IE 0 Bit 0 0 RESUME 0
Figure 11-3. USB Control Register USBEN -- USB Module Enable This read/write bit enables the USB module. Setting this bit updates the endpoint configuration according to the definition defined in UEPxCSR, UINTFCR, UEP12BPR and UEP34BPR registers. User must ensure the 48MHz clock source is ready before the module is enabled. When the USBEN bit is returned to zero, the module is reset and the device is returned to power state. User is recommended to reset all the status flags by software before enabling USBEN again. Reset clears this bit. 1 = USB module enabled 0 = USB module disabled USBCLKEN -- USB Clock Enable This read/write bit enables the 48MHz clock source to the USB module. User must ensure this bit is set before setting USBEN bit. In USB suspend mode it is recommended to clear this bit for power saving. Reset clears this bit. 1 = USB clock enabled 0 = USB clock disabled TCxIE -- Transfer complete interrupt enable for endpoint x The read/write bit enables CPU interrupt when transfer complete flag (TFRC) of corresponding endpoint is set. TC0IE is controlling both TFRC0_IN and TFRC0_OUT at the same time. Reset clears this bit. 1 = Transfer complete interrupt enabled 0 = Transfer complete interrupt disabled RESUME -- Force RESUME condition This write-only bit forces a resume state (K or non-idle state) onto the USB bus data lines to initiate a remote wakeup. This bit generates RESUME only if the device is in SUSPEND mode and the remote wake up feature is enabled by the SET_FEATURE command. The USB control logic ensures the forced resume duration is greater than 3ms. Reading this bit always returns zero. Writing zero to the bit has no effect. 1 = Generates forced RESUME condition on the USB data lines 0 = Default value
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 153
USB 2.0 FS Module
11.5.2 USB Status Register (USBSR)
Address: Read: Write: Reset: 0 0 = Unimplemented $0052 Bit 7 CONFIG 6 5 SETUP 0 4 SOF 0 3 CONFIG_ CHG 0 2 USBRST 0 1 RESUMEF 0 Bit 0 SUSPND 0
Figure 11-4. USB Status Register CONFIG -- Configuration Number This read-only bit specify the configuration number returned from the USB host. The module only supports a single configuration setting. 1 = Device configure to configuration number 1 0 = Device is unconfigured SETUP -- SETUP Request Received This read/write bit indicates a valid GET_DESCRIPTOR command, SYNC_FRAME command or class/vendor specific request is detected. This bit only set when the packet is received without CRC/Token/EOP error. When this is set, user must read and decode the request from the endpoint 0 data registers (UE0D7-0). Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = GET_DESCRIPTOR, SYNC_FRAME or Class/vendor specific requests received 0 = No vendor specific request received SOF -- Start of Frame Detection Flag This read/write bit indicates a start-of-frame signal is detected from the USB data line. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = Start-of-frame is detected 0 = No start-of-frame is detected CONFIG_CHG -- Change of Configuration Detection Flag This read/write bit indicates a change of device configuration request is received from the host. This bit will be set when new configuration is requested and accepted by the host. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = A change of configuration request is received 0 = No change of configuration request is received USBRST -- USB Reset Detection Flag This read/write bit is set when a valid reset signal state is detected on the D+ and D- lines. If URSTD bit of the configuration register (CONFIG) is clear, this reset detection flag will generate a MCU internal reset signal to reset the CPU and its peripheral. Otherwise, if URSTD is set, a interrupt request will be generated instead. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = USB reset signal is detected 0 = No USB reset signal is detected RESUMEF -- RESUME Detection Flag This read/write bit is set when bus activity is detected while the device is in SUSPEND mode. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = USB bus activity is detected while the device is in SUSPEND mode 0 = No USB bus activity is detected
MC68HC908JW32 Data Sheet, Rev. 5 154 Freescale Semiconductor
USB Module Registers
SUSPND -- SUSPEND Detection Flag This read/write bit is set when the module detects a suspend state on the USB bus or the bus is idle for 3ms. The module will enter suspend mode when this bit is set. In order to reduce the power consumption, user is recommended to stop the USB module clock by clearing the USBCLKEN bit in USBCR register before putting the MCU in STOP mode. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit. 1 = SUSPEND state is detected 0 = No suspend state is detected
11.5.3 USB Status Interrupt Mask Register (USIMR)
Address: Read: Write: Reset: $0053 Bit 7 R 0 R 6 0
EP0_STALL
5 SETUPIE 0
4 SOFIE 0
3 CONFIG_ CHGIE 0
2 USBRESETIE 0
1 RESUMEFIE 0
Bit 0 SUSPNDIE 0
0 = Reserved
Figure 11-5. USB Status Interrupt Mask Register EP0_STALL -- Forced EP0 STALL Handshake Enable This write only bit is used to provide protocol STALL to the control endpoint. Writing one to the bit causes endpoint 0 to return STALL in response to any IN or OUT token issue by the USB host until the next SETUP transaction. The bit can only be erased by module hardware, writing zero to the bit has no effect. Reset also clears this bit. 1 = Send STALL handshake 0 = Do not response STALL handshaking SETUPIE -- SETUP Request Interrupt Mask This read/write bit enables a CPU interrupt request when GET_DESCRIPTOR, SYNC_FRAME or class/vendor specific request is received or SETUP flag of USB status register (USBSR) is set. Reset clears this bit. 1 = CPU interrupt is enabled when SETUP flag in USBSR is set 0 = CPU interrupt is disabled when SETUP flag in USBSR is set SOFIE -- Start-of-frame Interrupt Mask This read/write bit enables a CPU interrupt request when a start-of-frame signal is detected on the USB bus or SOF flag of USB status register (USBSR) is set. Reset clears this bit. 1 = SOF interrupt is enabled 0 = SOF interrupt is disabled CONFIG_CHGIE -- Configuration Change Interrupt Mask This read/write bit enables a CPU interrupt request when a configuration change from zero to one is detected or CONFIG_CHG flag of USB status register (USBSR) is set. Reset clears this bit. 1 = CPU interrupt is enabled when CONFIG_CHG flag in USBSR is set 0 = CPU interrupt is disabled when CONFIG_CHG flag in USBSR is set
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 155
USB 2.0 FS Module
USBRSTIE -- USB RESET Interrupt Mask This read/write bit enables a CPU interrupt request when USBRST flag of USB status register (USBSR) and URSTD bit of configuration register (CONFIG) is set. Reset clears this bit. 1 = CPU interrupt request is enabled when USB reset signal is detected 0 = CPU interrupt request is disabled when USB reset signal is detected RESUMEFIE -- Resume Interrupt Mask This read/write bit enables a CPU interrupt request when the USB bus activity is resumed or RESUMEF of USB status register (USBSR) is set. Reset clears this bit. 1 = CPU interrupt request is enabled when USB bus activity is resumed 0 = CPU interrupt request is disabled when USB bus activity is resumed SUSPNDIE -- Suspend Mode Interrupt Mask This read/write bit enables a CPU interrupt request when the module entered suspend mode or SUSPND flag of USB status register (USBSR) is set. Reset clears this bit. 1 = CPU interrupt request is enabled when the module enters suspend mode 0 = CPU interrupt request is disabled when the module enters suspend mode
11.5.4 USB Endpoint 0 Control/Status Register (UEP0CSR)
Address: $0054 Bit 7 6 5 4 3 DVALID_IN 0 2 TFRC_IN 0 1 DVALID_OUT 0 Bit 0 TFRC_OUT 0
Read: DSIZE3_OUT DSIZE2_OUT DSIZE1_OUT DSIZE0_OUT Write: Reset: DSIZE3_IN 0 DSIZE2_IN 0 DSIZE1_IN 0 DSIZE0_IN 0
Figure 11-6. USB Endpoint 0 Control/Status Register DSIZE[3:0]_OUT -- Endpoint 0 Data Size for OUT packet These bits specify the packet size received for the previous valid OUT packet. The bits are read only. DSIZE[3:0]_IN -- Endpoint 0 Data Size for IN packet These bits indicates the packet size to be transmitted in response to the next IN packet. The bits are write only. DVALID_IN -- Data valid enable bit for IN packet This read/write bit indicates the data in the endpoint buffer is valid and ready to send. Setting this bit triggers the data transmission. The bit will be cleared automatically by hardware when a successful IN packet transaction occurred or a valid SETUP packet is received. The bit can also be cleared by writing zero. When the bit is zero, all IN packets to endpoint zero will be responded by NAK. Reset also clears this bit. 1 = Data in the EP0 buffer is valid and ready to transmit 0 = Data in the EP0 buffer is not valid TFRC_IN -- Transfer Complete Flag for IN packet This read/write bit indicates the data in the EP0 buffer is completely transferred to the host. When the bit is set, all successive IN packet is responded by NAK. Writing zero to clear this bit. Writing one to the bit has no effect. 1 = Endpoint data transfer completed 0 = Default status
MC68HC908JW32 Data Sheet, Rev. 5 156 Freescale Semiconductor
USB Module Registers
DVALID_OUT -- Data valid enable bit for OUT packet This bit indicates valid data is stored in the endpoint buffer, CPU attention is required. User must clear this bit in order to receive the next OUT packet by writing zero to the bit, otherwise all successive OUT packet is NAK by the module. Writing one to the bit has no effect. Reset clears this bit. 1 = Data in the EP0 buffer is valid 0 = Data in the EP0 buffer is not valid TFRC_OUT -- Transfer Complete Flag for OUT packet This read/write bit indicates the a valid OUT or SETUP packet is completely transferred to the EP0 data buffer. When the bit is set, all successive OUT packet will be responded by NAK. Writing zero to clear this bit. Writing one to the bit has no effect. 1 = Endpoint data transfer completed 0 = Default status
11.5.5 USB Endpoint 1-4 Control Status Register (UEP1CSR-UEP4CSR)
Address: Read: Write: Reset: $0055 to $0058 Bit 7 MODE1 0 6 MODE0 0 5 0 STALL 0 4 DIR 0 3 SIZE1 0 2 SIZE0 0 1 DVALID 0 Bit 0 TFRC 0
Figure 11-7. USB Endpoint 1-4 Control Status Register TFRC -- Transfer Complete Flag This read/write bit indicates the data transfer associated with the endpoint is completed. When the bit is set, all successive IN/OUT packet will be responded by NAK. Writing zero to clear this bit. Writing one to the bit has no effect. 1 = Endpoint data transfer completed 0 = Default status DVALID -- Data valid bit When the endpoint is configured as IN endpoint, this bit indicates the data in the endpoint buffer is valid and ready to be sent. Setting this bit arms the data transmission otherwise all IN packets are returned by NAK. The bit will be cleared automatically by hardware when a successful IN packet transaction occurred. When the endpoint is configured as OUT endpoint, this bit indicates valid received data is stored in the endpoint buffer, CPU attention is required. User must clear this bit in order to receive the next OUT packet, otherwise all successive OUT packet is responded NAK by the module. Reset clears this bit. 1 = Data in the endpoint buffer is valid 0 = Data in the endpoint buffer is not valid
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 157
USB 2.0 FS Module
SIZE[1:0] -- Buffer size Selection bits This read/write bits select the buffer size for the corresponding endpoint. When USBEN is set, these bits has no effect. Table 11-4. Buffer Size Selection Table
SIZE[1:0] 00 01 10 11 Buffer Size 8 Bytes 16 Bytes 32 Bytes 64 Bytes
TFRCIE -- Transfer Complete Interrupt Enable This read/write bit enables the CPU interrupt associated with the TFRC flag. 1 = TFRC flag interrupt is enabled 0 = TFRC flag interrupt is disabled DIR -- Endpoint Direction Bit Setting this bit enables the endpoint to become IN endpoint. Clearing this bit enables the endpoint to become OUT endpoint. Writing to this bit will have no effect when USBEN is set. 1 = IN endpoint is enabled 0 = OUT endpoint is enabled STALL -- Forced STALL Handshake Enable This read/write bit causes endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB host. If the bit is set by software, when a data packet addressed to that endpoint is detected, this STALL status will be latched to the module, the bit is cleared automatically and the packet will be responded by STALL. Once the STALL status is latched, it can only be cleared by CLEAR_FEATURE command from the host. Software cannot clear this status. If there is no packet addressed to the endpoint after the bit is set, it can still be cleared by writing zero. Reset clears this bit. 1 = Send STALL handshake 0 = Do not response STALL handshaking NOTE When USB RESET is detected, explicitly writing zero to the STALL bit is recommended to ensure all unlatched STALL status is cleared. MODE[1:0] -- Endpoint Type selection This bit selects the type of the endpoint. When USBEN is set, this bit has no effect. Table 11-5. Mode selection for Endpoint type
MODE[1:0] 00 01 10 11 Endpoint Type Endpoint Disable -- Bulk Interrupt
MC68HC908JW32 Data Sheet, Rev. 5 158 Freescale Semiconductor
USB Module Registers
11.5.6 USB Endpoint 1-4 Data Size Register (UEP1DSR-UEP4DSR)
Address: Read: Write: Reset: 0 $0059 to $005C Bit 7 6 DSIZE6 0 = Unimplemented 5 DSIZE5 0 4 DSIZE4 0 3 DSIZE3 0 2 DSIZE2 0 1 DSIZE1 0 Bit 0 DSIZE0 0
Figure 11-8. USB Endpoint 1-4 Data Size Register DSIZE[6:0] -- Packet Data Size When the corresponding endpoint is configured as IN endpoint, these bits indicates the packet size to be transmitted. When the corresponding endpoint is configured as OUT endpoint, these bits indicates the packet size received.
11.5.7 USB Endpoint 1/2 and 3/4 Base Pointer Register (UEP12BPR-UEP34BPR)
Address: Read: Write: Reset: Read: Write: Reset: 0 0 $005D to $005E Bit 7 6 BASE22 0 BASE42 0 = Unimplemented 5 BASE21 0 BASE41 0 4 BASE20 0 BASE40 0 0 0 3 2 BASE12 0 BASE32 0 1 BASE11 0 BASE31 0 Bit 0 BASE10 0 BASE30 0
Figure 11-9. USB Endpoint 1-4 Data Pointer Register BASEx[2:0] -- Base Location Pointer There are total 64 bytes of dedicated RAM space assigned to the module, the addressable space is from address $1000 to $103F. User must allocated appropriate buffer area to the endpoint which matches with the packet size reported to the host. This register indicates the base address pointer for the endpoint buffer area. The pointer location must align to the 8 bytes boundary. BASEx[2:0] specifies only the 3 address bits A5-A3. When USBEN is set, these bit have no effect. Table 11-6. BASEx[2:0] Address Definition
%0001 0000 A15-A8 0 A7 0 A6 A5 BASEx[2:0] A4 A3 0 A2 0 A1 0 A0
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 159
USB 2.0 FS Module
11.5.8 USB Interface Control Register (UINTFCR)
Address: Read: Write: Reset: $005F Bit 7 6 EP4INT 0 0 0 = Unimplemented 5 4 EP3INT 0 0 3 2 EP2INT 0 0 1 Bit 0 EP1INT 0
Figure 11-10. USB Interface Control Register EP1INT -- Endpoint 1 Interface number This bit specifies the interface number for physical endpoint 1. The interface number is loaded to the USB module at the time when the USB module is enabled. When USBEN is set, this bit has no effect. Reset clears this bit. 1 = The interface number for endpoint 1 is one 0 = The interface number for endpoint 1 is zero EP2INT -- Endpoint 2 Interface number This bit specifies the interface number for physical endpoint 2. The interface number is loaded to the USB module at the time when the USB module is enabled. When USBEN is set, this bit has no effect. Reset clears this bit. 1 = The interface number for endpoint 2 is one 0 = The interface number for endpoint 2 is zero EP3INT -- Endpoint 3 Interface number This bit specifies the interface number for physical endpoint 3. The interface number is loaded to the USB module at the time when the USB module is enabled. When USBEN is set, this bit has no effect. Reset clears this bit. 1 = The interface number for endpoint 3 is one7 0 = The interface number for endpoint 3 is zero EP4INT -- Endpoint 4 Interface number This bit specifies the interface number for physical endpoint 4. The interface number is loaded to the USB module at the time when the USB module is enabled. When USBEN is set, this bit has no effect. Reset clears this bit. 1 = The interface number for endpoint 4 is one 0 = The interface number for endpoint 4 is zero
11.5.9 USB Endpoint 0 Data Register 7-0 (UE0D7-UE0D0)
Address: $0040 to $0047 UE0Dx6_ OUT UE0Dx6_ IN UE0Dx5_ OUT UE0Dx5_ IN UE0Dx4_ OUT UE0Dx4_ IN UE0Dx3_ OUT UE0Dx3_ IN UE0Dx2_ OUT UE0Dx2_ IN UE0Dx1_ OUT UE0Dx1_ IN UE0D0x_ OUT UE0Dx0_ IN
UE0Dx7_ Read: OUT Write: Reset: UE0Dx7_ IN
Unaffected by reset
Figure 11-11. USB Endpoint 0 Data Register 7-0 These are the IN/OUT data buffer endpoint 0. The OUT buffer can be accessed by reading to the registers. The IN buffer can be accessed by writing to the registers.
MC68HC908JW32 Data Sheet, Rev. 5 160 Freescale Semiconductor
Chapter 12 PS2 Clock Generator (PS2CLK)
12.1 Introduction
This module provides the capability to generate PS2 clock.
12.2 Functional Description
Figure 12-1 shows the block diagram for the PS2 clock generator. The module is enabled by setting PS2EN bit. When the module is enabled, the output port becomes an open-drain output. A two phase clock is created by the prescaler block, one is driving the clock generator unit and the other is driving the interrupt generator. The clock generator drives the output port directly if CLKEN bit is set, while the interrupt generator enables CPU interrupt at the different clock phase. The CPU interrupt can be masked by clearing the PS2IEN bit. The waveform diagram is shown in Figure 12-2. When the module is enabled, the output port status is continuous monitored and stored in PSTATUS flag.
PTE2/PS2CLK/D+
PSTATUS PS2IEN CLKEN PS2IF
CPU Interrupt
CLOCK GENERATOR
INTERRUPT GENERATOR
PS2EN PRE CSEL[1:0] PRESCALER Bus Clock
Figure 12-1. PS2 Clock Generator Block Diagram
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 161
PS2 Clock Generator (PS2CLK)
CLKEN = 1
CLKEN = 0
CLK Output
Interrupt Generator
CPU Interrupt Trigger
Figure 12-2. Clock Generator Output Waveform.
12.3 PS2 Clock Generator Control and Status Registers
Address: $0019 Bit 7 Read: PSTATUS Write: Reset: 0 6 PS2IF 0 5 PRE 0 4 CSEL1 0 3 CSEL0 0 R 2 PS2IEN 0 = Reserved 1 CLKEN 0 Bit 0 PS2EN 0
= Unimplemented
Figure 12-3. PS2 Clock Generator Control and Status Registers (PS2CSR) PSTATUS -- Port Status Flag This read only bit reflects the port status when the module is enabled. Reset clears this bit. 1 = Port status is logic high 0 = Port status is logic low PS2IF -- PS2 Interrupt Flag. This flag is set when PS2 interrupt is trigger by the interrupt generator. Writing one to this bit clears the flag. Reset clears this flag. 1 = CPU interrupt is pending 0 = CPU interrupt is not pending
MC68HC908JW32 Data Sheet, Rev. 5 162 Freescale Semiconductor
PS2 Clock Generator Control and Status Registers
PRE -- Prescaler Selection These bits select prescaler divider ratio. Reset clears this bit. 1 = Divide by 480 is selected 0 = Divide by 160 is selected CSEL[1:0] -- Clock Frequency Selection bits. These bits selects the clock divider ratio to cater for different clock source frequency. Reset clears these bits. Table 12-1. CSEL[1:0] Divider Ratio
CSEL[1:0] 00 01 10 11 Divider Ratio 1 2 4 Not used
Table 12-2. Clock Selection Summary
BUS Frequency 8-MHz 6-MHz 4-MHz PRE (Divider Raito) 160 480 160 CSEL[1:0] (Divider Ratio) 4 1 2 Port Output Frequency 12.5 kHz 12.5 kHz 12.5 kHz
NOTE Glitches may occur when CSEL[1:0] and PRE value can be altered while PS2EN is set. PS2IEN -- PS2 Interrupt Mask This read/write bit enables the periodic PS2 interrupt. Reset clears this bit. 1 = PS2 interrupt is enabled 0 = PS2 interrupt is disabled CLKEN -- Clock Output Enable bit This read/write bit enables the open drain clock output. Reset clears this bit. 1 = Open drain clock output is enabled 0 = Open drain clock output is disabled PS2EN -- PS2 Clock Generator Module Enable This read/write bit enables the module clock source. Reset clears this bit. 1 = Module enabled 0 = Module disabled
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 163
PS2 Clock Generator (PS2CLK)
MC68HC908JW32 Data Sheet, Rev. 5 164 Freescale Semiconductor
Chapter 13 Input/Output (I/O) Ports
13.1 Introduction
Twenty-nine (29) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: $0008 Port E Data Register Write: (PTE) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: Data Direction Register B Write: (DDRB) Reset: PTD7 PTD6 PTD5 Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset PTB5 Unaffected by reset PTC3 Unaffected by reset PTD4 PTD3 PTD2 PTD1 PTD0 PTC2 PTC1 PTC0 PTB1 PTB0
$0001
$0002
$0003
Unaffected by reset PTE7 PTE6 PTE5 PTE4 PTE3 PTE2
Unaffected by reset DDRA7 0 DDRA6 0 DDRA5 0 DDRB5 0 0 = Unimplemented 0 0 0 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 0 DDRB1 0 DDRA0 0 DDRB0 0
$0004
$0005
Figure 13-1. I/O Port Register Summary
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 165
Input/Output (I/O) Ports Addr. $0006 Register Name Read: Data Direction Register C Write: (DDRC) Reset: Read: Data Direction Register D Write: (DDRD) Reset: Read: Data Direction Register E Write: (DDRE) Reset: Port Option Control Read: Register 1 Write: (POCR1) Reset: Port Option Control Read: Register 2 Write: (POCR2) Reset: Read: Pullup Control Register Write: (PULLCR) Reset: 0 DDRD7 0 DDRE7 0 0 DDRD6 0 DDRE6 0 0 DDRD5 0 DDRE5 0 LEDB5 0 0 0 0 0 0 0 PTD7PD 0 PULL5EN 0 0 = Unimplemented 0 0 0 0 0 PTD3PD 0 0 PTD2PD 0 0 DPPULLEN 0 0 DDRD4 0 DDRE4 0 Bit 7 6 5 4 3 DDRC3 0 DDRD3 0 DDRE3 0 2 DDRC2 0 DDRD2 0 DDRE2 0 0 LEDB1 0 PTE3P 0 PULL1EN 0 0 LEDB0 0 PTE2P 0 PULL0EN 0 1 DDRC1 0 DDRD1 0 Bit 0 DDRC0 0 DDRD0 0
$0007
$0009
$001A
$001B
$003E
Figure 13-1. I/O Port Register Summary (Continued)
Table 13-1. Port Control Register Bits Summary
Port Bit
0 1 2 3 A 4 5 6 7 DDRA4 DDRA5 DDRA6 DDRA7
DDR
DDRA0 DDRA1 DDRA2 DDRA3
Module Control Module Register Control Bit
KBIE0 KBIE1 KBIE2 KBIE3 KBI KBIER ($17) KBIE4 KBIE5 KBIE6 KBIE7
Pin
PTA0/KBA0 PTA1/KBA1 PTA2/KBA2 PTA3/KBA3 PTA4/KBA4 PTA5/KBA5 PTA6/KBA6 PTA7/KBA7
MC68HC908JW32 Data Sheet, Rev. 5 166 Freescale Semiconductor
Introduction
Table 13-1. Port Control Register Bits Summary
Port Bit DDR Module Control Module
LED 0 DDRB0 PULLUP LED B 1 DDRB1 PULLUP LED 5 0 1 C 2 3 0 1 2 3 D 4 5 6 7 DDRD4 DDRD5 DDRD6 DDRD7 PULLUP USB 2 DDRE2 PULLUP PS2CLK USB 3 E IRQ 4 5 6 7 DDRE4 DDRE5 SPI DDRE6 DDRE7 SPCR ($4C) SPE PTE6/MISO PTE7/SS IOCR ($1C) PTE3IE PTE4/SPSCK PTE5/MOSI DDRE3 PULLUP POCR2 ($1B) USBCR ($51) POCR2 ($1B) PS2CSR ($19) USBCR ($51) POCR2 ($1B) PTD7PD USBEN PTE2P PS2EN USBEN PTE3P PTE3/D- PTE2/D+ -- -- -- PTD4 PTD5 PTD6 PTD7 DDRC2 DDRC3 DDRD0 DDRD1 DDRD2 PULLUP DDRD3 POCR2 ($1B) PTD3PD PTD3 -- -- -- T1SC1 ($13) -- -- -- ELS1B:ELS1A -- -- -- PTD2PD PTC2/T1CH1 PTC3 PTD0 PTD1 PTD2 DDRB5 PULLUP DDRC0 DDRC1 TIM1 PULLCR ($3E) T1SC0 ($10) T1SC ($0A) PULL5EN ELS0B:ELS0A PS[2:0] PTC0/T1CH0 PTC1/TCLK1 PULLCR ($3E) POCR1 ($1A) PULL1EN LEDB5 PTB5 PULLCR ($3E) POCR1 ($1A) PULL0EN LEDB1 PTB1
Register
POCR1 ($1A)
Control Bit
LEDB0
Pin
PTB0
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 167
Input/Output (I/O) Ports
13.2 Port A
Port A is an 8-bit general-purpose bidirectional I/O port with software configurable pullups, and it shares its pins with the keyboard interrupt module (KBI).
13.2.1 Port A Data Register
The port A data register contains a data latch for each of the eight port A pins.
Address: Read: Write: Reset: Alternative $0000 Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset KBA7 Optional pullup KBA6 Optional pullup KBA5 Optional pullup KBA4 Optional pullup KBA3 Optional pullup KBA2 Optional pullup KBA1 Optional pullup KBA0 Optional pullup
Function:
Additional Function:
Figure 13-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBA7-KBA0 -- Keyboard Interrupts The keyboard interrupt enable bits, KBA7-KBA0, in the keyboard interrupt enable register (KBIER), enable the port A pins as external interrupt pins and the internal pullup of the corresponding pin. (See Chapter 15 Keyboard Interrupt Module (KBI).)
13.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0004 Bit 7 DDRA7 0* 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
* DDRA7 bit is reset by POR or LVI reset only.
Figure 13-3. Data Direction Register A (DDRA)
MC68HC908JW32 Data Sheet, Rev. 5 168 Freescale Semiconductor
Port A
DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 13-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 13-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-2 summarizes the operation of the port A pins. Table 13-2. Port A Pin Functions
DDRA Bit 0 1 PTA Bit I/O Pin Mode Accesses to DDRA Read/Write X(1) X Input, Hi-Z(2) Output DDRA[7:0] DDRA[7:0] Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0]
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 169
Input/Output (I/O) Ports
13.3 Port B
Port B is a 3-bit general-purpose bidirectional I/O port; open-drain when configured as output.
13.3.1 Port B Data Register
The port B data register contains a data latch for each of the three port B pins.
Address: Read: Write: Reset: Additional Function: Additional Function: LED drive Optional pullup = Unimplemented $0001 Bit 7 6 5 PTB5 Unaffected by reset LED drive Optional pullup LED drive Optional pullup 4 3 2 1 PTB1 Bit 0 PTB0
Figure 13-5. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under control of the corresponding bit in data direction register B. Reset has no effect on port B data. LED Drive -- Direct LED Driver The LED direct drive bit, LEDB[7:0], in the port option control register (POCR) controls the drive options for PTB[7:0]. (See 13.7 Port Options.) Pullup -- Programmable Pullup The Pullup control bit, PULL[7:0]EN, in the pullup control register (PULLCR) controls the optional pullup for PTB[7:0]. (See 13.7 Port Options.)
13.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: = Unimplemented $0005 Bit 7 6 5 DDRB5 0 4 3 2 1 DDRB1 0 Bit 0 DDRB0 0
Figure 13-6. Data Direction Register D (DDRD)
MC68HC908JW32 Data Sheet, Rev. 5 170 Freescale Semiconductor
Port B
DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 13-7 shows the port B I/O circuit logic.
READ DDRD ($0007)
WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTBx PTBx DDRBx
READ PTD ($0003)
Figure 13-7. Port B I/O Circuit When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-3 summarizes the operation of the port B pins. Table 13-3. Port B Pin Functions
DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Accesses to DDRB Read/Write DDRB5,1,0 DDRB5,1,0 Accesses to PTB Read Pin PTB5,1,0 Write PTB5,1,0(3) PTB5,1,0
Output
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 171
Input/Output (I/O) Ports
13.4 Port C
Port C is a 4-bit general-purpose bidirectional I/O port. PTC[3:0] are shared with Timer.
13.4.1 Port C Data Register
The port C data register contains a data latch for each of the seven port C pins.
Address: Read: Write: Reset: Additional Function: = Unimplemented $0002 Bit 7 6 5 4 3 PTC3 Unaffected by reset T1CH1 T1CLK T1CH0 2 PTC2 1 PTC1 Bit 0 PTC0
Figure 13-8. Port C Data Register (PTC) Table 13-4 shows the port function priority table. Table 13-4. Port C Priority Table
MSxB:MSxA 01/10/11 00 Feature Timer function pins Port logic control
PTC[3:0] -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. T1CH0, T1CH1 -- Timer Channels I/O Bits The PTC0/T1CH0, PTC2/T1CH1 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether they are timer channel I/O pins or general-purpose I/O pins. (see Chapter 8 Timer Interface Module (TIM)) TCLK1 -- Timer Clock Input The PTC1/TCLK1 pin are the external clock input for the TIM. The prescaler select bits, PS[2:0], select PTC1/TCLK1 as the TIM clock input. When not selected as the TIM clock, they are available for general purpose I/O. (see Chapter 8 Timer Interface Module (TIM)) NOTE Data direction register C (DDRC) does not affect the data direction of port C pins that are being used by the TIM. However, the DDRC bits always determine whether reading port C returns the states of the latches or the states of the pins.
MC68HC908JW32 Data Sheet, Rev. 5 172 Freescale Semiconductor
Port C
13.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented $0006 Bit 7 6 5 4 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
Figure 13-9. Data Direction Register C (DDRC) DDRC[3:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[3:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 3. Figure 13-10 shows the port C I/O logic.
READ DDRC ($0007)
WRITE DDRC ($0007) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 13-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port C pins. Table 13-5. Port C Pin Functions
DDRC Bit 0 1 PTC Bit X
(1)
I/O Pin Mode Input, Hi-Z Output
(2)
Accesses to DDRC Read/Write DDRC[3:0] DDRC[3:0]
Accesses to PTC Read Pin PTC[3:0] Write PTC[3:0](3) PTC[3:0]
X
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 173
Input/Output (I/O) Ports
13.5 Port D
Port D is a 8-bit general-purpose bidirectional I/O port.
13.5.1 Port D Data Register
The port D data register contains a data latch for each of the eight port D pins.
Address: Read: Write: Reset: Additional Function: Optional Pullup = Unimplemented $0003 Bit 7 PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0
Unaffected by reset Optional Pullup Optional Pullup
Figure 13-11. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under control of the corresponding bit in data direction register D. Reset has no effect on port D data. PTD2, PTD3 and PTD7 There is programmable pullup associated with the pins. The pullup are default enabled and can be controlled via POCR2 register.
13.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0007 Bit 7 DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0
Figure 13-12. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1.
MC68HC908JW32 Data Sheet, Rev. 5 174 Freescale Semiconductor
Port D
Figure 13-13 shows the port D I/O circuit logic.
READ DDRD ($0008)
WRITE DDRD ($0008) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
Figure 13-13. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-6 summarizes the operation of the port D pins. Table 13-6. Port D Pin Functions
DDRD Bit 0 1 PTD Bit I/O Pin Mode Accesses to DDRD Read/Write X(1) X Input, Hi-Z(2) Output DDRD[7:0] DDRD[7:0] Accesses to PTD Read Pin PTD[7:0] Write PTD[7:0](3) PTD[7:0]
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 175
Input/Output (I/O) Ports
13.6 Port E
Port E is a 6-bit general-purpose bidirectional I/O port. PTE[3:2] are special-function pins that share with the USB data pin D+ and D-. Four of the pins PTE[7:4] are shared with serial peripheral interface (SPI) module.
13.6.1 Port E Data Register
The port E data register contains a data latch for each of the six port E pins.
Address: Read: Write: Reset: Alternative Function: $0008 Bit 7 PTE7 6 PTE6 5 PTE5 4 PTE4 3 PTE3 2 PTE2 1 Bit 0
Unaffected by reset D- D+
Additional Function:
high high current current open drain open drain Optional USB pullup to VREF33 Optional 5k pullup to VDD External Interrupt PS2CLK SS MISO MOSI SPSCK Optional 5k pullup to VDD
Additional Function:
Additional Function:
Additional Function: Additional Function: Additional Function:
= Unimplemented
Figure 13-14. Port E Data Register (PTE)
MC68HC908JW32 Data Sheet, Rev. 5 176 Freescale Semiconductor
Port E
Table 13-7 shows the priority table for PTE2/D+ pin. Table 13-7. PTE2/D+ Priority Table
USB Module Enable (USBEN) 1 1 0 0 0 0 0 0 PS2 Clock Generator Enable (PS2EN) X X 1 1 0 0 0 0 Data Direction Control (DDRE2) X X X X 1 1 0 0 5k Pullup Enable (PTE2P) X X 1/0 0 X 1 X 1 USB D+ Pullup Enable (DPPULPEN) 1 0 0 1/0 1 0 1 0
Pin Function
D+ with pullup to VREF33. D+ without pullup PS2 Clock output (open-drain) with optional 5k pullup to VDD PS2 Clock output (open-drain) with optional 1.2k pullup to VREG33 GPIO output (open-drain) with 1.2K pullup to REG33V GPIO output (open-drain) with 5k pullup to VDD GPIO input with 1.2K pullup to REG33V GPIO input with 5K pullup to VDD
Table 13-8 shows the priority table for PTE3/D- pin. Table 13-8. PTE3/D- Priority Table
USB Module Enable (USBEN) 1 0 0 0 PTE3 IRQ Enable (PT3IE) X 1 0 0 Data Direction Control (DDRE3) X X 0 1 5K Pullup Enable (PTE3P) X 0/1 0/1 0/1 USB D- pin GPIO input with associated interrupt function and optional 5k pullup to VDD GPIO input with optional 5k pullup to VDD GPIO output (open-drain) with optional 5k pullup to VDD Pin Function
PTE[7:2] -- Port E Data Bits PTE[7:2] are read/write, software-programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. The PTE3 and PTE2 pullup enable bits, PTE3P and PTE2P, in the port option control register 2 (POCR2) enable 5k pullups to VDD on PTE3 and PTE2 if the USB module is disabled. (See 13.7 Port Options.) The PTE2 USB pullup enable bits, DPPULLEN, in the port option control register 2 (POCR2) enable USB pullups to VREF33 on PTE2 for USB operation. Either of PTE2P or DPPULLEN bit can be activated at the one time, DPPULLEN bit has higher priority, it will always override the setting of PTE2P bit.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 177
Input/Output (I/O) Ports
PTE3 pin functions as an external interrupt when PTE3IE=1 in the IRQ option control register (IOCR) and USBEN=0 in the USB address register (USB disabled). (See 14.7 IRQ Status and Control Register.) PTE2 pin also muxed with PS2 clock generator module. (See Chapter 12 PS2 Clock Generator (PS2CLK).) D- and D+ -- USB Data Pins D- and D+ are the differential data lines used by the USB module. (See Chapter 11 USB 2.0 FS Module.) When the USB module is enabled, PTE2/D+ and PTE3/D- function as USB data pins D- and D+. When the USB module is disabled, PTE2/D+ and PTE3/D- function as open drain high current pins for PS/2 clock and data use. NOTE PTE2/D+ pin has two programmable pullup resistors. One is used for PTE2 when the USB module is disable and another is used for D+ when the USB module is enabled. Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 13-5. Port C Pin Functions.) SS, MISO, MOSI, and SPSCK -- SPI Functional Pins These are the chip select, master-input-slave-output, master-output-slave-input and clock pins for the SPI module. The SPI enable bit, SPE, in the SPI control register, SPCR, enables these pins as the SPI functional pins and overrides any control from port I/O logic. See Chapter 10 Serial Peripheral Interface Module (SPI).
13.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0009 Bit 7 DDRE7 0 6 DDRE6 0 5 DDRE5 0 4 DDRE4 0 3 DDRE3 0 2 DDRE2 0 0 0 1 Bit 0
= Unimplemented
Figure 13-15. Data Direction Register E (DDRE) DDRE[7:2] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:2], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1.
MC68HC908JW32 Data Sheet, Rev. 5 178 Freescale Semiconductor
Port E
Figure 13-16 shows the port E I/O circuit logic.
READ DDRE ($0009)
WRITE DDRE ($0009) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 13-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-9 summarizes the operation of the port E pins.
Table 13-9. Port E Pin Functions
DDRE Bit 0 1 PTE Bit X(1) X I/O Pin Mode Accesses to DDRE Read/Write Input, Hi-Z(2) Output DDRE[7:2] DDRE[7:2] Accesses to PTE Read Pin PTE[7:2] Write PTE[7:2](3) PTE[7:2]
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 179
Input/Output (I/O) Ports
13.7 Port Options
All pins of port B have programmable pullup resistors and LED drive capability. Port pins have programmable high current drive capability.
13.7.1 Port Option Control Register 1
Address: Read: Write: Reset: 0 0 $001A Bit 7 6 5 LEDB5 0 0 0 0 4 3 2 1 LEDB1 0 Bit 0 LEDB0 0
= Unimplemented
Table 13-10. port Option Control Register 1 (POCR1) LEDB[5,1,0] -- Port B LED Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port B pin configured for direct LED drive: high current sinking capability 0 = Corresponding port B pin configured for standard drive
13.7.2 Port Option Control Register 2
The port option control register controls the pullup options for port E.
Address: Read: Write: Reset:
0 0 = Unimplemented $001B Bit 7 0 6 0 5 PTD7PD 0 4 PTD3PD 0 3 PTD2PD 0 2 DPPULLEN 0 1 PTE3P 0 Bit 0 PTE2P 0
Table 13-11. Port Option Control Register 2 (POCR2) PTD7PD -- Pin PTD7 Pullup Disable This read/write bit disables the pullup option for pin PTD7. The pullup resistor is default enabled after reset. 1 = Pullup option disabled 0 = Pullup option enabled PTD3PD -- Pin PTD3 Pullup Disable This read/write bit disables the pullup option for pin PTD3. The pullup resistor is default enabled after reset. 1 = Pullup option disabled 0 = Pullup option enabled PTD2PD -- Pin PTD2 Pullup Disable This read/write bit disables the pullup option for pin PTD2. The pullup resistor is default enabled after reset. 1 = Pullup option disabled 0 = Pullup option enabled
MC68HC908JW32 Data Sheet, Rev. 5 180 Freescale Semiconductor
Port Options
DPPULLEN -- D+ Pullup Enable This read/write bit enables the USB D+ pullup option to VREF33 for pin PTE2. 1 = Configure PTE2 to have internal USB pullups to VREF33 0 = Disconnect PTE2 internal pullups PTE3P -- Pin PTE3 Pullup Enable This read/write bit enables the pullup option for pin PTE3 if it is not configured as an USB D- pin or USB module is disabled. 1 = Configure PTE3 to have 5k internal pullups 0 = Disconnect PTE3 internal pullups PTE2P -- Pin PTE2 Pullup Enable This read/write bit enables the pullup option for pin PTE2 if it is not configured as an USB D+ pin or USB module is disabled. 1 = Configure PTE2 to have 5k internal pullups 0 = Disconnect PTE2 internal pullups NOTE When the USB module is enabled, the pullup controlled by PTE2P and PTE3P are disconnected; PTE2/D+ pin functions as D+ which has a programmable pull-up resistor by setting the DPPULLEN bit.
13.7.3 Pullup Control Register (PULLCR)
The pullup control register enables the embedded pullup resistor associated with port B [5,1,0].
Address: Read: Write: Reset: 0 0 $003E Bit 7 6 5 PULL5EN 0 0 0 0 4 3 2 1 PULL1EN 0 Bit 0 PULL0EN 0
= Unimplemented
Figure 13-17. Pullup Control Register (PULLCR)
PULL[5,1,0]EN -- Pullup Enable Bit This read/write bits enables the embedded pullup resistor associated with the corresponding port pin. Reset clears this bit. 1 = Pullup resistor is enabled 0 = Pullup resistor is disabled
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 181
Input/Output (I/O) Ports
MC68HC908JW32 Data Sheet, Rev. 5 182 Freescale Semiconductor
Chapter 14 External Interrupt (IRQ)
14.1 Introduction
The IRQ module provides two external interrupt inputs: one dedicated IRQ pin and one shared port pin, PTE3/D-.
14.2 Features
Features of the IRQ module include: * Two external interrupt pins, IRQ and PTE3/D- * IRQ interrupt control bits * Hysteresis buffer * Programmable edge-only or edge and level interrupt sensitivity * Automatic interrupt acknowledge * Low leakage IRQ pin for external RC wake up input * Selectable internal pullup resistor
14.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 14-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. * Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch. * Reset -- A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or low-level-triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * Vector fetch or software clear * Return of the interrupt pin to logic one
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 183
External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 6.5 Exception Control.)
INTERNAL ADDRESS BUS
ACK RESET VECTOR FETCH DECODER HIGH VOLTAGE DETECT TO MODE SELECT LOGIC TO CPU FOR BIL/BIH INSTRUCTIONS
VDD IRQPD "1"
INTERNAL
PULLUP DEVICE
IRQF D CLR Q SYNCHRONIZER
IRQ
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
TO PTE3 PULLUP ENABLE CIRCUITRY
MODE
"1" D PTE3 CLR Q
READ IOCR PTE3IF
CK
PTE3IE
Figure 14-1. IRQ Module Block Diagram
MC68HC908JW32 Data Sheet, Rev. 5 184 Freescale Semiconductor
IRQ Pin
Addr. $001C
Register Name IRQ Option Control Register (IOCR) Read: Write: Reset:
Bit 7 0 0 0 0
6 0 0 0 0
5 0 0 0 0
4 0 0 0 0
3 0 0 IRQF 0
2 PTE3IF 0 0 ACK 0
1 PTE3IE 0 IMASK 0
Bit 0 IRQPD 0 MODE 0
$001E
IRQ Status and Control Register (ISCR)
Read: Write: Reset:
= Unimplemented
Figure 14-2. IRQ I/O Register Summary
14.4 IRQ Pin
The IRQ pin has a low leakage for input voltages ranging from 0V to VDD; suitable for applications using RC discharge circuitry to wake up the MCU. A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFF8 and $FFF9. * Return of the IRQ pin to logic one -- As long as the IRQ pin is at logic zero, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE An internal pullup resistor to VDD is connected to IRQ pin; this can be disabled by setting the IRQPD bit in the IRQ option control register ($001C).
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 185
External Interrupt (IRQ)
14.5 PTE3/D- Pin
The PTE3 pin is configured as an interrupt input to trigger the IRQ interrupt when the following conditions are satisfied: * The USB module is disabled * PTE3 pin configured for external interrupt input (PTE3IE = 1) Setting PTE3IE configures the PTE3 pin to an input pin with an internal pullup device. The PTE3 interrupt is "ORed" with the IRQ input to trigger the IRQ interrupt Figure 14-1. Therefore, the IRQ status and control register affects both the IRQ pin and the PTE pin. An interrupt on PTE3 also sets the PTE3 interrupt flag, PTE3IF, in the IRQ option control register (IOCR).
14.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Chapter 6 System Integration Module (SIM).) To allow software to clear the IRQIRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
14.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has the following functions: * Shows the state of the IRQ flag * Clears the IRQ latch * Masks IRQ interrupt request * Controls triggering sensitivity of the IRQ pin
Address: Read: Write: Reset: 0 0 0 0 0 = Unimplemented $001E Bit 7 0 6 0 5 0 4 0 3 IRQF 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 14-3. IRQ Status and Control Register (ISCR) IRQF -- IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending
MC68HC908JW32 Data Sheet, Rev. 5 186 Freescale Semiconductor
IRQ Option Control Register
ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
14.8 IRQ Option Control Register
The IRQ option control register controls and monitors the external interrupt function available on the PTE3 pin. It also disables/enables the pullup resistor on the IRQ pin. * Controls pullup option on IRQ pin * Enables PTE3 pin for external interrupts to IRQ * Shows the state of the PTE3 interrupt flag
Address: Read: Write: Reset: 0 0 0 0 0 0 = Unimplemented $001C Bit 7 0 6 0 5 0 4 0 3 0 2 PTE3IF 1 PTE3IE 0 Bit 0 IRQPD 0
Figure 14-4. IRQ Option Control Register (IOCR) PTE3IF -- PTE3 Interrupt Flag This read-only status bit is high when a falling edge on PTE3 pin is detected. PTE3IF bit clears when the IOCR is read. 1 = falling edge on PTE3 is detected and PTE3IE is set 0 = falling edge on PTE3 is not detected or PTE3IE is clear PTE3IE -- PTE3 Interrupt Enable This read/write bit enables or disables the interrupt function on the PTE3 pin to trigger the IRQ interrupt. Setting the PTE3IE bit and clearing the USBEN bit in the USB address register configure the PTE3 pin for interrupt function to the IRQ interrupt. Setting PTE3IE also enables the internal pullup on PTE3 pin. 1 = PTE3 interrupt enabled; triggers IRQ interrupt 0 = PTE3 interrupt disabled IRQPD -- IRQ Pullup Disable This read/write bit controls the pullup option for the IRQ pin. 1 = Internal pullup is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 187
External Interrupt (IRQ)
MC68HC908JW32 Data Sheet, Rev. 5 188 Freescale Semiconductor
Chapter 15 Keyboard Interrupt Module (KBI)
15.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7 pins.
15.2 Features
Features of the keyboard interrupt module include: * Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask * Hysteresis buffers * Programmable edge-only or edge- and level-interrupt sensitivity * Exit from low-power modes
Addr. $0016 Register Name Keyboard Status Read: and Control Register Write: (KBSCR) Reset: Keyboard Interrupt Enable Read: Register Write: (KBIER) Reset: Bit 7 0 0 KBIE7 0 6 0 0 KBIE6 0 = Unimplemented 5 0 0 KBIE5 0 4 0 0 KBIE4 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
$0017
Figure 15-1. KBI I/O Register Summary
15.3 Pin Name Conventions
The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 15-1. The generic pin name appear in the text that follows. Table 15-1. Pin Name Conventions
KBI Generic Pin Name KBA0-KBA7 Full MCU Pin Name PTA0/KBA0-PTA7/KBA7 Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE0-KBIE7
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 189
Keyboard Interrupt Module (KBI)
15.4 Functional Description
INTERNAL BUS
KBA0 VREG . KBIE0 TO PULLUP ENABLE . KBA7 . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request
CK
KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE7 TO PULLUP ENABLE
Figure 15-2. Keyboard Module Block Diagram Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. * If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. NOTE To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. * Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
MC68HC908JW32 Data Sheet, Rev. 5 190 Freescale Semiconductor
Functional Description
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
15.4.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the pullup device to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 191
Keyboard Interrupt Module (KBI)
15.5 I/O Registers
These registers control and monitor operation of the keyboard module: * Keyboard status and control register (KBSCR) * Keyboard interrupt enable register (KBIER)
15.5.1 Keyboard Status and Control Register
The keyboard status and control register: * Flags keyboard interrupt requests * Acknowledges keyboard interrupt requests * Masks keyboard interrupt requests * Controls keyboard interrupt triggering sensitivity
Address: Read: Write: Reset: 0 0 0 0 0 = Unimplemented $0016 Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Figure 15-3. Keyboard Status and Control Register (KBSCR) KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
MC68HC908JW32 Data Sheet, Rev. 5 192 Freescale Semiconductor
Low-Power Modes
15.5.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin.
Address: Read: Write: Reset: $0017 Bit 7 KBIE7 0 6 KBIE6 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
Figure 15-4. Keyboard Interrupt Enable Register (KBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin
15.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
15.6.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
15.6.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
15.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See Figure 15-3. Keyboard Status and Control Register (KBSCR).)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 193
Keyboard Interrupt Module (KBI)
MC68HC908JW32 Data Sheet, Rev. 5 194 Freescale Semiconductor
Chapter 16 Computer Operating Properly (COP)
16.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
16.2 Functional Description
Figure 16-1 shows the structure of the COP module.
SIM CGMRCLK 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR STAGES 5-12
CLEAR ALL STAGES
INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG) CLEAR COP COUNTER
Figure 16-1. COP Block Diagram
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 195
COP TIMEOUT
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMRCLK cycles, depending on the state of the COP rate select bit, COPRS in the configuration register. With a 262,128 CGMRCLK cycle overflow option (COPRS = 0), a 4-MHz external clock source gives a COP timeout period of 66ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 CGMRCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
16.3 I/O Signals
The following paragraphs describe the signals shown in Figure 16-1.
16.3.1 CGMRCLK
CGMRCLK is the reference clock output from the OSC module. If a 4-MHz crystal is used, CGMRCLK is also 4-MHz.
16.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
16.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 16.4 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.
16.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the COP prescaler 4096 CGMRCLK cycles after power-up.
16.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
MC68HC908JW32 Data Sheet, Rev. 5 196 Freescale Semiconductor
COP Control Register
16.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler.
16.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
16.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register (CONFIG).
Address: Read: Write: Reset: $001F Bit 7 COPRS 0 6 LVISTOP 0 = Unimplemented 5 LVIRSTD 0 4 LVIPWRD 0 0 3 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Figure 16-2. Configuration Register (CONFIG) COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (8176) x CGMRCLK cycles 0 = COP timeout period is (262,128) x CGMRCLK cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
16.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: Read: Write: Reset: $FFFF Bit 7 6 5 4 3 2 1 Bit 0 Low byte of reset vector Clear COP counter Unaffected by reset
Figure 16-3. COP Control Register (COPCTL)
16.5 Interrupts
The COP does not generate CPU interrupt requests.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 197
Computer Operating Properly (COP)
16.6 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin or on the RST pin.
16.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
16.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
16.7.2 Stop Mode
Stop mode turns off the CGMRCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
16.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908JW32 Data Sheet, Rev. 5 198 Freescale Semiconductor
Chapter 17 Low-Voltage Inhibit (LVI)
17.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the VDD pin, and can force a reset when VDD voltage falls below VTRIPF1.
17.2 Features
Features of the LVI module include: * Independent voltage monitoring circuits for VDD * Independent LVI circuit disable for VDD * Programmable LVI reset * Programmable stop mode operation
Addr. $FE0F Register Name Read: LVI Status Register Write: (LVISR) Reset: Bit 7 LVIOUT 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 17-1. LVI I/O Register Summary
17.3 Functional Description
Figure 17-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains independent bandgap reference circuit and comparator for monitoring the VDD voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide low-voltage protection to external peripheral devices. LVISTOP, LVIPWRD, LVIRSTD are in the CONFIG1 register. See Chapter 3 Configuration Registers (CONFIG) for details of the LVI configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above VTRIPR1 which causes the MCU to exit reset. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 199
Low-Voltage Inhibit (LVI)
VDD STOP INSTRUCTION LVISTOP FROM CONFIG1
LVIPWRD FROM CONFIG1 LOW VDD DETECTOR VDD > VTRIPR1 = 0 VDD VTRIPF1 = 1
FROM CONFIG1 LVIRSTD
LVI RESET
LVIOUT TO LVISR
Figure 17-2. LVI Module Block Diagram
17.3.1 Low VDD Detector
The low VDD detector circuit monitors the VDD voltage and forces a LVI reset when the VDD voltage falls below the trip voltage, VTRIPF1. The VDD LVI circuit can be disabled by the setting the LVIPWRD bit in CONFIG1 register.
17.3.2 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF1 level, software can monitor VDD by polling the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
17.3.3 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF1 level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF1 level. In the CONFIG1 register, the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
17.3.4 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF1), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR1. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF1. VTRIPR1 is greater than VTRIPF1 by the hysteresis voltage, VHYS.
MC68HC908JW32 Data Sheet, Rev. 5 200 Freescale Semiconductor
LVI Status Register
17.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below VTRIPF1.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 $FE0F Bit 7 LVIOUT 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0
Figure 17-3. LVI Status Register LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD or VREG falls below their respective trip voltages. Reset clears the LVIOUT bit. Table 17-1. LVIOUT Bit Indication
VDD, VREG VDD > VTRIPR1 VDD < VTRIPF1 VTRIPF1 < VDD < VTRIPR1 LVIOUT 0 1 Previous value
17.5 LVI Interrupts
The LVI module does not generate interrupt requests.
17.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode.
17.6.2 Stop Mode
If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode. If enabled to generate resets (LVIRSTD = 0), the LVI module can generate a reset and bring the MCU out of stop mode.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 201
Low-Voltage Inhibit (LVI)
MC68HC908JW32 Data Sheet, Rev. 5 202 Freescale Semiconductor
Chapter 18 Break Module (BRK)
18.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
18.2 Features
Features of the break module include: * Accessible input/output (I/O) registers during the break interrupt * CPU-generated break interrupts * Software-generated break interrupts * COP disabling during break interrupts
Addr. Register Name Bit 7 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 BCFE 0 Bit 15 0 Bit 7 0 BRKE 0 14 0 6 0 BRKA 0 13 0 5 0 0 12 0 4 0 0 11 0 3 0 0 10 0 2 0 0 9 0 1 0 0 Bit 8 0 Bit 0 0 0 R R R R R R R Bit 0 R
Read:
$FE00 SIM Break Status Register Write: (SBSR)
R
Reset:
$FE03 SIM Break Flag Control Register Write: (SBFCR) Break Address Register High Write: (BRKH) Break Address Register Low Write: (BRKL) Break Status and Control Register Write: (BRKSCR)
Read:
Reset: Read:
$FE0C
Reset: Read:
$FE0D
Reset: Read:
$FE0E
Reset:
0
0
0
0
0
0
Note: Writing a logic 0 clears BW.
= Unimplemented
R
= Reserved
Figure 18-1. Break Module I/O Register Summary
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 203
Break Module (BRK)
18.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. * Software writes a logic 1 to the BRKA bit in the break status and control register. When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 18-2 shows the structure of the break module.
IAB15-IAB8
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15-IAB0 CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK
IAB7-IAB0
Figure 18-2. Break Module Block Diagram
18.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state.
18.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction * Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
18.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
MC68HC908JW32 Data Sheet, Rev. 5 204 Freescale Semiconductor
Low-Power Modes
18.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the RST pin.
18.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
18.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set. (See Chapter 6 System Integration Module (SIM).) Clear the BW bit by writing logic 0 to it.
18.4.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
18.5 Break Module Registers
These registers control and monitor operation of the break module: * Break status and control register (BRKSCR) * Break address register high (BRKH) * Break address register low (BRKL) * SIM break status register (SBSR) * SIM break flag control register (SBFCR)
18.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: Read: Write: Reset: $FE0E Bit 7 BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 18-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 205
Break Module (BRK)
BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match
18.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: Read: Write: Reset: $FE0C Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0
Figure 18-4. Break Address Register High (BRKH)
Address: Read: Write: Reset: $FE0D Bit 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
Figure 18-5. Break Address Register Low (BRKL)
18.5.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
Address: Read: Write: Reset: Note: Writing a logic 0 clears SBSW. R = Reserved $FE00 Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R
Figure 18-6. SIM Break Status Register (SBSR)
SBSW -- Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it.
MC68HC908JW32 Data Sheet, Rev. 5 206 Freescale Semiconductor
Break Module Registers
18.5.4 SIM Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 18-7. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 207
Break Module (BRK)
MC68HC908JW32 Data Sheet, Rev. 5 208 Freescale Semiconductor
Chapter 19 Electrical Specifications
19.1 Introduction
This section contains electrical and timing specifications.
19.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 19.5 DC Electrical Characteristics for guaranteed operating conditions. Table 19-1. Absolute Maximum Ratings(1)
Characteristic Supply voltage Input voltage All pins (except IRQ) IRQ pin Maximum current per pin excluding VDD and VSS Maximum current out of VSS Maximum current into VDD Storage temperature 1. Voltages referenced to VSS. Symbol VDD VIN Value -0.3 to +6.0 Unit V
VSS -0.3 to VDD +0.3 VSS -0.3 to 8.5 25 100 100 -55 to +150
V
I IMVSS IMVDD TSTG
mA mA mA C
NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 209
Electrical Specifications
19.3 Functional Operating Range
Table 19-2. Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value 0 to +70 3.5 to 5.5 Unit C V
19.4 Thermal Characteristics
Table 19-3. Thermal Characteristics
Characteristic Thermal resistance 48-Pin QFN I/O pin power dissipation Power dissipation(1) Symbol JA PI/O PD Value 84 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) Unit C/W W W
Constant(2) Average junction temperature
K TJ
W/C C
1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908JW32 Data Sheet, Rev. 5 210 Freescale Semiconductor
DC Electrical Characteristics
19.5 DC Electrical Characteristics
Table 19-4. DC Electrical Characteristics
Characteristic(1) 2.5V Regulator Output Voltage 3.3V Regulator Output Voltage (At VDD from 3.9V-5.5V)(3) Output high voltage (ILOAD = -2.0 mA) All ports Output low voltage (ILOAD = 1.6mA) All ports Output Sourcing Capability PTB0-PTB1 (VOL = 0.4V) PTB5 (VOL = 0.4V) PTE2-PTE3 (VOL = 0.4V) Input high voltage All ports, RST, IRQ Input low voltage All ports, RST, IRQ VDD supply current Run(4) (0C-70C), fOP = 8 MHz (all modules on including USB) Wait(5) (0C-70C), fOP = 8 MHz (all modules on including USB) Stop (0C-70C) with RC on, LVI on and all other modules off Stop (0C-70C) with RC off, LVI on and all other modules off Digital I/O ports Hi-Z leakage current All ports, RST Input current IRQ Capacitance Ports (as input or output) POR rise-time ramp rate(6) POR assert voltage(7) Monitor mode entry voltage (at IRQ pin) -- -- IDD -- -- IIL IIN COUT CIN RPOR VPOR_assert VTST -- -- -- -- 0.035 0.90 1.5 x VDD -- -- -- -- -- -- -- 1.62 -- 350 280 10 1 12 8 -- 2.1 8 A A A A -- -- 18 16 mA mA Symbol VREG25 VREG33 Min 2.25 3.0 Typ(2) 2.5 3.3 Max 2.75 3.6 Unit V V
VOH VOL
VDD -0.8 --
--
--
V
--
0.4
V
ILOAD
18 12 8 0.7 x VDD VSS
26 18 12 -- --
34 24 16 VDD 0.3 x VDD
mA mA mA V V
VIH VIL
pF V/ms V V
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 211
Electrical Specifications
Table 19-4. DC Electrical Characteristics (Continued)
Characteristic(1) Pullup resistors(8) PTA0-PTA7 configured as KBI0-KBI7 RST, IRQ, PTD2, PTD3, PTD7 PTE2-PTE3 with USB disabled PTE2/D+ with USB enabled (to REG33V)(9) PTE3/D- with USB enabled (to REG33V)(10) PTB0-PTB1, PTB5 with internal pullup enabled Low-voltage inhibit for external VDD, trip falling voltage (kick-in) Low-voltage inhibit for external VDD, trip rising voltage (recovery) Symbol Min Typ(2) Max Unit
RPU1 RPU2 RPU3 RPU4(Idle) RPU4(Tran) RPU5 VTRIPF1 VTRIPR1
21 21 4 900 1425 21 3.0 3.07
30 30 5 -- -- 30 3.3 3.4
39 39 6 1575 3090 39 3.5 3.6
k k k k V V
1. VDD = 3.9 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. When VDD drops below 3.9V, the VREF33 regulator output will not be guaranteed within 3.3V +/- 10%. 4. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 5. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 6. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 7. The internal 2.5V regulator has embedded a LVI_POR circuitry when the regulator voltage drops below VLVI_POR_assert voltage it triggers the CPU reset. The reset is released when the regulator voltage returns above VLVI_POR_release voltage. 8. RPU1 and RPU2 are measured at VDD = 5.0V 9. The resistor value is measured at VDD = 3.9 to 5.5 Vdc, VSS = 0 Vdc. 10. The resistor value is measured at VDD = 3.9 to 5.5 Vdc, VSS = 0 Vdc.
19.6 Control Timing
Table 19-5. Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 750 Max 8 -- Unit MHz ns
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
19.7 Internal RC Clock Timing
Table 19-6. Internal RC Clock Timing
Characteristic(1) Internal RC Clock frequency Symbol fOP Min 74 TYP 88 Max 105 Unit kHz
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
MC68HC908JW32 Data Sheet, Rev. 5 212 Freescale Semiconductor
Crystal Oscillator Characteristics
19.8 Crystal Oscillator Characteristics
Table 19-7. Oscillator Characteristics
Characteristic Crystal frequency(1) External clock Reference frequency(1), (2) Crystal load capacitance(3) Crystal fixed capacitance(3) Crystal tuning capacitance(3) Feedback bias resistor Series resistor(3), (4) Symbol fXCLK fXCLK CL C1 C2 RB RS Min 1 dc -- -- -- -- -- Typ -- -- -- 2 x CL 2 x CL 10 M -- Max 4 4 -- -- -- -- -- Unit MHz MHz
1. The USB module is designed to function at fXCLK = 4MHz. 2. No more than 10% duty cycle deviation from 50%. 3. Consult crystal vendor data sheet. 4. Not required for high-frequency crystals.
19.9 USB DC Electrical Characteristic
The USB electrical performance is compliant to the USB specification 2.0. Table 19-8. USB DC Electrical Characteristics
Characteristic(1) Hi-Z state data line leakage Voltage input high (driven) Voltage input high (floating) Voltage input low Differential input sensitivity Differential common mode range Static output low Static output high Output signal crossover voltage Regulator bypass capacitor Regulator bulk capacitor Symbol ILO VIH VIHZ VIL VDI VCM VOL VOH VCRS CREGBYPASS CREGBULK 4.7 |(D+) - (D-)| Includes VDI Range RL of 1.425 K to 3.6 V RL of 14.25 K to GND 2.8 1.3 -- 0.47 0.2 0.8 2.5 0.3 3.6 2.0 Conditions 0V1. VDD = 3.9 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 213
Electrical Specifications
19.10 Timer Interface Module Characteristics
Table 19-9. Timer Interface Characteristics
Characteristic Input capture pulse width Symbol tTIH, tTIL Min 1 Max -- Unit tCYC
19.11 FLASH Program/Erase Timing
Table 19-10. Flash Program/Erase Timing
Characteristic PROG/ERASE to NVSTR setup time NVSTR hold time NVSTR hold time (mass erase) NVSTR to program setup time Program Time Page Erase Time Mass Erase Time Recovery time Accumulative program HV period Symbol Tnvs Tnvh Tnvhl Tpgs Tprog Terase Tme Trcv Thv Min 5 5 100 10 20 20 200 1 -- Max -- -- -- -- 40 -- -- -- 8 Unit s s s s s ms ms s ms
19.12 CGM Electrical Specifications
Table 19-11. CGM Electrical Specifications
Characteristic Operating Voltage Reference frequency VCO center-of-range frequency VCO multiply factor VCO prescale multiplier Reference divider factor VCO operating frequency Manual acquisition time Automatic lock time Symbol VDD fRDV fVRS N 2P R fVCLK tLOCK tLOCK Min 3.5 -- -- 1 0 1 24 -- -- Typ -- 4 48M -- -- 1 -- -- -- Max 5.5 -- -- 6 1 1 48 5 5 MHz ms ms Unit V MHz Hz
MC68HC908JW32 Data Sheet, Rev. 5 214 Freescale Semiconductor
5.0V SPI Characteristics
19.13 5.0V SPI Characteristics
Table 19-12. SPI Characteristics
Diagram Number(1) Characteristic(2) Operating frequency Master Slave Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit
fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S)
fOP/128 dc
fOP/2 fOP
MHz MHz
1
2 1 1 1
128 -- -- --
tCYC tCYC tCYC tCYC
2 3
4
tCYC - 25 1/2 tCYC - 25 tCYC - 25 1/2 tCYC - 25
64 tCYC --
ns ns
5
64 tCYC --
ns ns
6
30 30
-- --
ns ns
7
30 30
-- --
ns ns
8
0 0 --
40 40 40
ns ns ns
9
10
-- --
50 50
ns ns
11
0 0
-- --
ns ns
1. Numbers refer to dimensions in Figure 19-1 and Figure 19-2. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 215
Electrical Specifications
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
NOTE
5 4
SPSCK OUTPUT CPOL = 1
NOTE
5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT
MISO INPUT
MSB IN 11
BITS 6-1
MOSI OUTPUT
MASTER MSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
5 4
NOTE
SPSCK OUTPUT CPOL = 1
5 4 6 7 LSB IN 10 BITS 6-1 MASTER LSB OUT
NOTE
MISO INPUT 10 MOSI OUTPUT
MSB IN 11 MASTER MSB OUT
BITS 6-1
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 19-1. SPI Master Timing
MC68HC908JW32 Data Sheet, Rev. 5 216 Freescale Semiconductor
5.0V SPI Characteristics
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 5 4 3
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 19-2. SPI Slave Timing
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 217
Electrical Specifications
MC68HC908JW32 Data Sheet, Rev. 5 218 Freescale Semiconductor
Chapter 20 Ordering Information and Mechanical Specifications
20.1 Introduction
This section contains ordering information for the MC68HC908JW32. In addition, this section gives the package dimensions for the 48-pin quad flat non-leaded package.
20.2 Ordering Information
Table 20-1. MC Order Numbers
MC Order Number MCHC908JW32FC Package 48-pin QFN Operating Temperature Range 0 to +70 C
20.3 Package Dimensions
Refer to the following pages for detailed package dimensions.
MC68HC908JW32 Data Sheet, Rev. 5 Freescale Semiconductor 219
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MC68HC908JW32 Rev. 5, 10/2006

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